EGGH92: Eurographics Workshop on Graphics Hardware 1992

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https://diglib.eg.org/handle/10.2312/343

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On the Design of a Real-Time Volume Rendering Engine
(The Eurographics Association, 1992) Smit, J.; Wessels, N.J.; Horst, A. van del'; Bentum, M.J.; P F Lister
An architecture for a Real-Time Volume Rendering Engine is given capable of computing750x750x512 samples from a 3D dataset at a rate of 25 images per second.The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16RISe-processors. An plane interpolator circuit and a composition circuit, both capableto operate at very high speeds, have been designed for a 1.6 micron VLSI process.The interpolator is now back from production. It has been tested an complied withour specifications."
Anti-Aliased Line Drawing on a Distributed Cell Store System
(The Eurographics Association, 1992) Moore, A. A.; Ng, C. M.; Bustard, D. W.; Lister, P. F.
One of the principle drawbacks with traditional parallel image composition architectures is the lack of support for transparent images. This paper introduces the Distributed Cell Store System, an architecture based on image composition principles, but which provides explicit support for transparency via its Serial Bus System. The transparency support is exploited ina scheme for the generation of smooth-edged lines,which avoids the need for any anti-aliasing calculation in software. The benefits of segmenting lines so that different segments may be rendered in parallel in different processing units are identified and quantified, and the paper concludes with a discussion on the benefits for incremental image specification systems which could be gained from implementation on such a hardware platform."
Parallelization and Hardware Support for Ray Tracing
(The Eurographics Association, 1992) Groene, Alwin; Renz, Oliver; P F Lister
Even on the latest workstations ray tracing is still a very time-consuming algorithm.This paper makes a thorough analysis of previous attempts to accelerate raytracing by means of parallelization with general purpose processors and by means of designing special purpose processors. Since much work has been done concurrently by many researchers, only the most important milestones are mentioned. The conclusionsdrawn are quite different from those in many other papers.
ASICs for a High Performance IVIulti Processor Systemfor Photo-realistic Image Synthesis
(The Eurographics Association, 1992) Vijt, Peter De; Claesen, Luc; Man, Hugo De; P F Lister
A number of ASIC architectures are presented to build a system for fast photorealistic rendering of complex images. Both ray tracing and radiosity algorithms can be used. The system consists of a number of custom and general purpose processors that communicate through a serial interface. The scene database is split into three disjoint data sets. Rays are passed between processors. The load is dynamically balanced by means of a load balancing processor. Fine grain and coarse grain parallelismare exploited.
Hardware Challenges for Ray Tracing and Radiosity Algorithms
(The Eurographics Association, 1992) Jansen, Frederik W.; Kok, Arjan J. F.; Verelst, Theo; P F Lister
Computer graphics algorithms and graphics hardware have mainly been developed along two lines: real-time display and realistic display. Real-time display has been achieved by developing dedicated hardware for projective, depth-buffer display algorithms.Increased realism has been achieved by ray tracing and radiosity algorithms,which generally are implemented on standard workstations because the complexity of the computation makes it difficult to implement these algorithms in hardware. Inthis paper we review these different approaches and discuss the feasibility of usingspecial hardware to enhance the radiosity and ray tracing computation. In particularwe will explore the use of the intersection of a frustrum of rays with patches in a sceneas a basic computational primitive for these algorithms and their implementation inhardware.K eywords and phrases: rendering, radiosity, ray tracing, graphics hardware, parallelprocessing.
An Extended Volume Visualization System for Arbitrary Parallel Projection
(The Eurographics Association, 1992) Bakalash, R.; Kaufman, A.; Pacheco, R.; Pfister, H.; P F Lister
We present a special architecture for arbitrary parallel projection for visualization ofvolumetric data. Using a ray-casting technique, parallel memory access, and pipelinedprocessing of rays in a composition tree, we can achieve interactive rendering ratesfor a 5123 dataset."
An Efficient Massively Parallel Rasterization Scheme For a High Performance Graphics System
(The Eurographics Association, 1992) Karpf, S.; Chaillou, C.; P F Lister
We present in this paper the IMOGENE II system, a massively parallelMulti-SIMD graphics system. This architecture uses a new rasterization scheme combining Object Parallelism and Parallel Virtual Buffers. This scheme leads to a better efficiency than other massively parallel SHvlD systems, and allows a cost-effective, powerful and easily expandable system to be designed. The system consists of several SIMD ScanConversionPipelines each connected to a Multi-Level Virtual Buffer, a Shading Unitcomputing true Phong Shading, a Virtual Accumulation Frame Buffer for anti-aliasing,and a. classical Frame Buffer.
A 2nd generation autostereoscopic 3-D display
(The Eurographics Association, 1992) Lang, S.R.; Travis, A.R.L.; Castle, O.M.; Moore, l.R.; P F Lister
Hidden contours on a frame-buffer
(The Eurographics Association, 1992) Rossignac, Jarek R.; Emmerik, Maarten van; P F Lister
To comply with drafting practices and because shaded images do not always reveal the internal or hiddenstructures of 3D models, designers need wireframe images with hidden lines dashed and nonconlour tesselation edges removed. Software techniques for wireframe rendering of polyhedra that require the viewpoint-dependent identilication of the visible portions of intersection and contour (i.e. silhouette)edges are too slow for interactive applications. Hardware support in contemporary graphics pipelines is unavailable or at best limited to the identification of contour edges. In this paper, new hardware assisted techniques for hidden-line removal and determination of contour edges are presented. The techniques do not require any face/edge adjacency information and can be implemented easily on any platform that supports a hardware z-buffer.
An Architecture for Interactive Raster Graphics
(The Eurographics Association, 1992) Kuijk, A.A.M.; Blake, E.H.; Hagen, P.J.W. ten; P F Lister
A radical reappraisal of the 3-D Interactive raster graphics pipeline has resulted In an experimentalarchitecture for a workstation which is currently being evaluated at the CWI. The principal features of thisarchitecture are that It:- concentrates exclusively on real-time interactive 3-D graphics (initially for CAD).- uses object space rather than Image space methods where possible.- avoids using a frame buffer.- only uses custom VLSI where commercial products are unlikely to suffice In the near term.Four years Into the proJect the system design Is complete and the major components have been acquired andthe custom VLSI chips hove been packaged and tested. The current experience with the system is based ondetailed simulations which gave a fairiy clear Idea on Its strengths and limitations. A complete, but reducedresolution, experimental prototype system is now being assembled."
A Parallel-Pipelined Multiprocessor System for the Radiosity Method
(The Eurographics Association, 1992) Shen, L.S.; Deprettere, E.F.; P F Lister
Ray-tracing and radiosity algorithms can produce very realistic images, but they require a lot of computations which make them impractical for scenes of highcomplexity. Several attempts have been made to speed up computations through parallel processing. To get orders of magnitude speedup, massive parallelism involving multiplestreams will be necessary. In this paper, a parallel-pipelined multiprocessor system is described, which is made of clusters of specialized computing modules, each constructed of aDIntersection Computation Unit (lCU) and a number of Cell Traversal Units (CTUs). Both ICU and CTU are of type pipeline and with data-driven execution. A pseudo-dynamicscheduling is used to reconfigure the system at run time so that the workloads distributed over clusters can be more or less balanced. Furthermore, a hierarchical memory structure is proposed to reduce the average loading time of patches. Performance evaluation has been done and 15% more speedup can be obtained as observed by queueing networksimulation. A complete system level simulation is under way by using BONeS which is ablock oriented network simulator.
Distributed Frame Buffer for Rapid Dynamic Changes to 3D Scenes
(The Eurographics Association, 1992) Coppen, Derek; Slater, Mel; Davison, Allan; Hawes, David; P F Lister
This paper describes a distributed frame buffer architecture, based on the Tiling Algorithm for dynamic modification, and designed to achieve fast display updates inresponse to dynamic transformations of graphical objects. We report on the overall architecture and some detailed design issues.
Depth Complexity in Object-Parallel Graphics Architectures
(The Eurographics Association, 1992) Cox, Michael; Hanrahan, Pat; P F Lister
We consider a multiprocessor graphics architecture object-parallel if graphics primitivesare assigned to processors without regard to screen location, and if each processorcompletely renders the primitives it is assigned. Such an approach leads tothe following problem: the images rendered by all processors must be merged, orcomposited, before they can be displayed. At worst, the number of pixels that mustbe merged is a frame per processor. Perhaps there is a more parsimonious approachto pixel merging in object-parallel architectures than merging a full frame from eachprocessor.In this paper we analyze the number of pixels that must be merged in object-parallelarchitectures. Our analysis is from the perspective that the number of pixels to bemerged is a function of the depth complexity of the graphics scene to be rendered,and a function of the depth complexity of each processor's subset of the scene tobe rendered. We derive a model of depth complexity of graphics scenes rendered onobject-parallel architectures. The model is based strictly on the graphics primitivesize distribution, and on number of processors. \Ve validate the model with tracedata from a number of graphics applications, and with trace-driven simulations ofrendering on object-parallel architectures.The results of our analysis suggest some directions in design of object-parallel architectures,and suggest that our model can be used in future analysis of designtrade-offs in these architectures."
M-Buffer: A Flexible MISD Architecture for AdvancedGraphics
(The Eurographics Association, 1992) Schneider, Bengt-Olaf; Rossignac, Jarek; P F Lister
Contemporary graphics architectures are based on a hardware-supported geometric pipeline, a rasterizer, a z-buffer and two frame buffers. Additional pixel memory isused for alpha blending and for storing logical information. Although their functionality is growing it is still limited because of the fixed use of pixel memory and there stricted set of operations provided by these architectures. A new class of graphicsalgorithms that considerably extends the current technology is based on a moreflexible use of pixel memory, not supported by current architectures.The M-Buffer architecture described here divides pixel memory into general-purposebuffers, each associated with one processor. Pixel data is broadcast to all buffers simultaneously. Logical and numeric tests are performed by each processor and theresults are broadcast and used by all buffers in parallel to evaluate logical expressionsfor the pixel update condition.The architecture is scalable by addition of buffer-processors, suitable for pixel parallelization,and permits the use of buffers for different purposes. The architecture, its functional description, and a powerful programming interface are described.
Transputer-based Parallel Ray Tracing System Using Demand Data Transfer
(The Eurographics Association, 1992) Kawai, Toshiyuki; Ohnishi, Mitsuhisa; Abeki, Jun-ichi; Ohnishi, Hironobu; P F Lister
This paper describes a parallel ray tracing system MAGG which has 86 transputers and HDTV frame buffers. Our system is based on a screen subdivision algorithm. In this algorithm, each processor essentially requires entire scene database. Therefore huge local storage should be required if the scene is complicated. In order to avoid this,shape descriptions in a scene database should be transferred to the processor whenthey are required. However, it would lead to lower parallel processing performance.We have devised fast communication between the large shared memory and the localmemory on each processor by means of DMA transfer instead of serial link transfer. Some experimental results indicate it is effective to improve the efficiency of parallel processing.
Hardware Acceleration of Texture Mapping
(The Eurographics Association, 1992) Dunnett, Graham; Grimsdale, Richard; Lister, Paul; White, Martin; P F Lister
We present a hardware design based around scan-line algorithms. The design can perform colour mapping, environment mapping and produce shading effects which include a specular term. We describe the algorithms which are implemented, and the approximations we have made to achieve near real-time performance.
Accelerating Polygon Clipping
(The Eurographics Association, 1992) Schneider, Bengt-Olaf; P F Lister
Polygon clipping is a central part of image generation and image visualization systems.In spite of its algorithmic simplicity it consumes a considerable amount of hardware or software resources. Polygon clipping performance is dominated by two processes: intersection calculations and data transfers. The paper analyzes the prevalent Sutherland-Hodgman algorithm for polygon clippingand identifies cases for which this algorithm performs inefficiently. Such casesare characterized by subsequent vertices in the input polygon that share a commonregion, e. g. a common halfspace.The paper will present new techniques that detect such constellations and simplifythe input polygon such that the Sutherland-Hodgman algorithm runs more efficiently. Block diagrams and pseudo-code demonstrate that the new techniques are well suited for both hardware and software implementations. Finally, the paper discusses the results of a prototype implementation of the presented techniques. The analysis compares the performance of the new techniquesto the traditional Sutherland-Hodgman algorithm for different test scenes. The new techniques reduce the number data transfers by up to 90 % and the number of intersection calculations by up to 60 %.

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