On the Design of a Real-Time Volume Rendering Engine

Smit, J.; Wessels, N.J.; Horst, A. van del'; Bentum, M.J.

On the Design of a Real-Time Volume Rendering Engine

Files

070-076.pdf (459.37 KB)

Date

1992

Authors

Smit, J.
Wessels, N.J.
Horst, A. van del'
Bentum, M.J.

Publisher

The Eurographics Association

Abstract

An architecture for a Real-Time Volume Rendering Engine is given capable of computing750x750x512 samples from a 3D dataset at a rate of 25 images per second.The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16RISe-processors. An plane interpolator circuit and a composition circuit, both capableto operate at very high speeds, have been designed for a 1.6 micron VLSI process.The interpolator is now back from production. It has been tested an complied withour specifications."

        @inproceedings{:10.2312/EGGH/EGGH92/070-076
,
booktitle = {Eurographics Workshop on Graphics Hardware
},
editor = {P F Lister
},
title = {{On the Design of a Real-Time Volume Rendering Engine
}},
author = {Smit, J. and 
Wessels, N.J. and 
Horst, A. van del' and 
Bentum, M.J.
},
year = {1992
},
publisher = {The Eurographics Association
},
ISSN = {-
},
ISBN = {-
},
DOI = {/10.2312/EGGH/EGGH92/070-076
}
}