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dc.contributor.authorInada, Tetsugoen_US
dc.contributor.authorMcCool, Michael D.en_US
dc.contributor.editorMarc Olano and Philipp Slusalleken_US
dc.date.accessioned2013-10-28T10:04:58Z
dc.date.available2013-10-28T10:04:58Z
dc.date.issued2006en_US
dc.identifier.isbn3-905673-37-1en_US
dc.identifier.issn1727-3471en_US
dc.identifier.urihttp://dx.doi.org/10.2312/EGGH/EGGH06/111-120en_US
dc.description.abstractA number of texture compression algorithms have been proposed to reduce texture storage size and bandwidth requirements. To deal with the requirement for random access, these algorithms usually divide the texture into tiles and apply a fixed rate compression scheme to each tile. Fixed rate schemes are by nature lossy, and cannot adapt to local changes in image complexity. Multiresolution schemes, a form of variable-rate coding, can adapt to varying image complexity but suffer from fragmentation and can only compress a limited class of images. On the other hand, several lossless image compression standards have been established. Lossless compression requires variable-rate coding, and more efficient lossy algorithms also use variable-rate coding. Unfortunately, these standards cannot be used directly as texture compression schemes since they do not allow random access. We present a block-oriented lossless texture compression algorithm based on a simple variable-bitrate differencing scheme. A B-tree index enables both random access and efficient O(1) memory allocation without external fragmentation. Textures in our test suite compressed to between 6% and 95% of their original sizes. We propose a cache architecture designed to support our compression scheme. Cycle-accurate simulation shows that this cache architecture consistently reduces the external bandwidth requirements as well as the storage size without significantly affecting latency.en_US
dc.publisherThe Eurographics Associationen_US
dc.subjectCategories and Subject Descriptors (according to ACM CCS): I.3.1 [Computer Graphics]: Hardware Architecture- Graphics processorsen_US
dc.titleCompressed Lossless Texture Representation and Cachingen_US
dc.description.seriesinformationGraphics Hardwareen_US


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