A Hardware Processing Unit for Point Sets

dc.contributor.authorHeinzle, Simonen_US
dc.contributor.authorGuennebaud, Gaƫlen_US
dc.contributor.authorBotsch, Marioen_US
dc.contributor.authorGross, Markusen_US
dc.contributor.editorDavid Luebke and John Owensen_US
dc.date.accessioned2013-10-28T10:19:24Z
dc.date.available2013-10-28T10:19:24Z
dc.date.issued2008en_US
dc.description.abstractWe present a hardware architecture and processing unit for point sampled data. Our design is focused on fundamental and computationally expensive operations on point sets including k-nearest neighbors search, moving least squares approximation, and others. Our architecture includes a configurable processing module allowing users to implement custom operators and to run them directly on the chip. A key component of our design is the spatial search unit based on a kd-tree performing both kNN and eN searches. It utilizes stack recursions and features a novel advanced caching mechanism allowing direct reuse of previously computed neighborhoods for spatially coherent queries. In our FPGA prototype, both modules are multi-threaded, exploit full hardware parallelism, and utilize a fixed-function data path and control logic for maximum throughput and minimum chip surface. A detailed analysis demonstrates the performance and versatility of our design.en_US
dc.description.seriesinformationGraphics Hardwareen_US
dc.identifier.isbn978-3-905674-09-5en_US
dc.identifier.issn1727-3471en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH08/021-031en_US
dc.publisherThe Eurographics Associationen_US
dc.subjectCategories and Subject Descriptors (according to ACM CCS): I.3.1 [Hardware Architecture]: Graphics processorsen_US
dc.titleA Hardware Processing Unit for Point Setsen_US
Files
Original bundle
Now showing 1 - 1 of 1
Loading...
Thumbnail Image
Name:
021-031.pdf
Size:
1012.35 KB
Format:
Adobe Portable Document Format