Designing a half toning coprocessor

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dc.contributor.authorKugler, Aen_US
dc.contributor.authorHersch, R Den_US
dc.contributor.editorP. F. Lister and R. L. Grimsdaleen_US
dc.date.accessioned2014-02-06T14:24:18Z
dc.date.available2014-02-06T14:24:18Z
dc.date.issued1993en_US
dc.description.abstractHalftoning is a fairly slow process when executedby software on conventional processors. To speed uphalf toning, a half toning algorithm has been developed andintegrated into a dedicated hardware architecture. Thispaper describes the implementation of the architecturewith a XILINX Field Programmable Gate Array (FPGA)and compares its performances with results obtained by asoftware implementation. A discussion on how to improvethe present architecture concludes the paper.en_US
dc.description.seriesinformationEurographics Workshop on Graphics Hardwareen_US
dc.identifier.isbn-en_US
dc.identifier.issn-en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH93/113-118en_US
dc.publisherThe Eurographics Associationen_US
dc.titleDesigning a half toning coprocessoren_US
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EGGH93: Eurographics Workshop on Graphics Hardware 1993