Designing a half toning coprocessor

Kugler, A; Hersch, R D

Designing a half toning coprocessor

Files

113-118.pdf (2.89 MB)

Date

1993

Authors

Kugler, A
Hersch, R D

Publisher

The Eurographics Association

Abstract

Halftoning is a fairly slow process when executedby software on conventional processors. To speed uphalf toning, a half toning algorithm has been developed andintegrated into a dedicated hardware architecture. Thispaper describes the implementation of the architecturewith a XILINX Field Programmable Gate Array (FPGA)and compares its performances with results obtained by asoftware implementation. A discussion on how to improvethe present architecture concludes the paper.

        @inproceedings{:10.2312/EGGH/EGGH93/113-118
,
booktitle = {Eurographics Workshop on Graphics Hardware
},
editor = {P. F. Lister and R. L. Grimsdale
},
title = {{Designing a half toning coprocessor
}},
author = {Kugler, A and 
Hersch, R D
},
year = {1993
},
publisher = {The Eurographics Association
},
ISSN = {-
},
ISBN = {-
},
DOI = {/10.2312/EGGH/EGGH93/113-118
}
}