Single Chip Hardware Support for Rasterization and Texture Mapping

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dc.contributor.authorAckermann, Hans-Josefen_US
dc.contributor.editorW. Strasseren_US
dc.date.accessioned2014-02-06T14:30:47Z
dc.date.available2014-02-06T14:30:47Z
dc.date.issued1995en_US
dc.description.abstractToday's interactive 3D-applications on Pes demand efficient hardware support for functionality, e.g. shading and texture mapping. In this paper, I present an ASIC that integrates most of the 3D-reIated functionality defined in Intel's de-facto standard 3DR. As the chip was designed for real time environmental simulation systems, the main focus has been on texture mapping, which provides the most natural appearance at a moderate effort level. To avoid artifacts during texture mapping, the chip performs bi- or tri-linear blending on a MIPmap structure. Texture addresses are calculated perspective correct. A crucial problem concerning the tri-linear blending is the necessary data bandwidth between ASIC and the texture buffer. Therefore, I discuss several memory types and architectures for the texture buffer depending on performance, price and board space requirements. A short overview of different system architectures using the ASIC concludes the paper.en_US
dc.description.seriesinformationTenth Eurographics Workshop on Graphics Hardwareen_US
dc.identifier.isbn-en_US
dc.identifier.issn-en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH95/015-024en_US
dc.publisherThe Eurographics Associationen_US
dc.titleSingle Chip Hardware Support for Rasterization and Texture Mappingen_US
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EGGH95: Eurographics Workshop on Graphics Hardware 1995