Single Chip Hardware Support for Rasterization and Texture Mapping

Ackermann, Hans-Josef

Single Chip Hardware Support for Rasterization and Texture Mapping

Files

015-024.pdf (969.32 KB)

Date

1995

Authors

Ackermann, Hans-Josef

Publisher

The Eurographics Association

Abstract

Today's interactive 3D-applications on Pes demand efficient hardware support for functionality, e.g. shading and texture mapping. In this paper, I present an ASIC that integrates most of the 3D-reIated functionality defined in Intel's de-facto standard 3DR. As the chip was designed for real time environmental simulation systems, the main focus has been on texture mapping, which provides the most natural appearance at a moderate effort level. To avoid artifacts during texture mapping, the chip performs bi- or tri-linear blending on a MIPmap structure. Texture addresses are calculated perspective correct. A crucial problem concerning the tri-linear blending is the necessary data bandwidth between ASIC and the texture buffer. Therefore, I discuss several memory types and architectures for the texture buffer depending on performance, price and board space requirements. A short overview of different system architectures using the ASIC concludes the paper.

        @inproceedings{:10.2312/EGGH/EGGH95/015-024
,
booktitle = {Tenth Eurographics Workshop on Graphics Hardware
},
editor = {W. Strasser
},
title = {{Single Chip Hardware Support for Rasterization and Texture Mapping
}},
author = {Ackermann, Hans-Josef
},
year = {1995
},
publisher = {The Eurographics Association
},
ISSN = {-
},
ISBN = {-
},
DOI = {/10.2312/EGGH/EGGH95/015-024
}
}