Bandwidth-Efficient BVH Layout for Incremental Hardware Traversal

dc.contributor.authorLiktor, Gaboren_US
dc.contributor.authorVaidyanathan, Karthiken_US
dc.contributor.editorUlf Assarsson and Warren Hunten_US
dc.date.accessioned2016-06-17T14:07:15Z
dc.date.available2016-06-17T14:07:15Z
dc.date.issued2016en_US
dc.description.abstractThe memory footprint of bounding volume hierarchies (BVHs) can be significantly reduced using incremental encoding, which enables the coarse quantization of bounding volumes. However, this compression alone does not necessarily yield a comparable improvement in memory bandwidth. While the bounding volumes of the BVH nodes can be aggressively quantized, the size of the child node pointers remains a significant overhead. Moreover, as BVH nodes become comparably small to practical cache line sizes, the BVH is cached less efficiently. In this paper we introduce a novel memory layout and node addressing scheme and map it to a system architecture for fixed-function ray traversal. We evaluate this scheme using an architecture simulator and demonstrate a significant reduction in memory bandwidth, compared to previous approaches.en_US
dc.description.sectionheadersBetter BVHsen_US
dc.description.seriesinformationEurographics/ ACM SIGGRAPH Symposium on High Performance Graphicsen_US
dc.identifier.doi10.2312/hpg.20161192en_US
dc.identifier.isbn978-3-03868-008-6en_US
dc.identifier.issn2079-8679en_US
dc.identifier.pages51-61en_US
dc.identifier.urihttps://doi.org/10.2312/hpg.20161192en_US
dc.publisherThe Eurographics Associationen_US
dc.subjectI.3.1 [Computer Graphics]en_US
dc.subjectHardware Architectureen_US
dc.subjectGraphics processorsen_US
dc.subjectI.3.3 [Computer Graphics]en_US
dc.subjectThree Dimensional Graphics and Realismen_US
dc.subjectRaytracingen_US
dc.titleBandwidth-Efficient BVH Layout for Incremental Hardware Traversalen_US
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