Bandwidth-Efficient BVH Layout for Incremental Hardware Traversal

Liktor, Gabor; Vaidyanathan, Karthik

Bandwidth-Efficient BVH Layout for Incremental Hardware Traversal

Files

051-061.pdf (3.4 MB)

Date

2016

Authors

Liktor, Gabor
Vaidyanathan, Karthik

Publisher

The Eurographics Association

Abstract

The memory footprint of bounding volume hierarchies (BVHs) can be significantly reduced using incremental encoding, which enables the coarse quantization of bounding volumes. However, this compression alone does not necessarily yield a comparable improvement in memory bandwidth. While the bounding volumes of the BVH nodes can be aggressively quantized, the size of the child node pointers remains a significant overhead. Moreover, as BVH nodes become comparably small to practical cache line sizes, the BVH is cached less efficiently. In this paper we introduce a novel memory layout and node addressing scheme and map it to a system architecture for fixed-function ray traversal. We evaluate this scheme using an architecture simulator and demonstrate a significant reduction in memory bandwidth, compared to previous approaches.

        @inproceedings{10.2312:hpg.20161192
,
booktitle = {Eurographics/ ACM SIGGRAPH Symposium on High Performance Graphics
},
editor = {Ulf Assarsson and Warren Hunt
},
title = {{Bandwidth-Efficient BVH Layout for Incremental Hardware Traversal
}},
author = {Liktor, Gabor and 
Vaidyanathan, Karthik
},
year = {2016
},
publisher = {The Eurographics Association
},
ISSN = {2079-8679
},
ISBN = {978-3-03868-008-6
},
DOI = {10.2312/hpg.20161192
}
}