Reduced Precision for Hardware Ray Tracing in GPUs
| dc.contributor.author | Keely, Sean | en_US |
| dc.contributor.editor | Ingo Wald and Jonathan Ragan-Kelley | en_US |
| dc.date.accessioned | 2015-07-06T15:26:31Z | |
| dc.date.available | 2015-07-06T15:26:31Z | |
| dc.date.issued | 2014 | en_US |
| dc.description.abstract | We propose a high performance, GPU integrated, hardware ray tracing system. We present and make use of a new analysis of ray traversal in axis aligned bounding volume hierarchies. This analysis enables compact traversal hardware through the use of reduced precision arithmetic. We also propose a new cache based technique for scheduling ray traversal. With the addition of our compact fixed function traversal unit and cache mechanism, we show that current GPU architectures are well suited for hardware accelerated ray tracing, requiring only small modifications to provide high performance. By making use of existing GPU resources we are able to keep all rays and scheduling traffic on chip and out of caches. We used simulations to estimate the performance of our architecture. Our system achieves an average ray rate of 3.4 billion rays per second while path tracing our test scenes. | en_US |
| dc.description.seriesinformation | Eurographics/ ACM SIGGRAPH Symposium on High Performance Graphics | en_US |
| dc.identifier.isbn | 978-3-905674-60-6 | en_US |
| dc.identifier.issn | 2079-8679 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.2312/hpg.20141091 | en_US |
| dc.identifier.uri | https://diglib.eg.org:443/handle/10.2312/hpg.20141091 | |
| dc.publisher | The Eurographics Association | en_US |
| dc.subject | I.3.1 [Computer Graphics] | en_US |
| dc.subject | Hardware Architecture | en_US |
| dc.subject | Graphics processors | en_US |
| dc.subject | I.3.7 [Computer Graphics] | en_US |
| dc.subject | Three Dimensional Graphics and Realism | en_US |
| dc.subject | Raytracing | en_US |
| dc.title | Reduced Precision for Hardware Ray Tracing in GPUs | en_US |
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