SaarCOR - A Hardware Architecture for Ray Tracing
| dc.contributor.author | Schmittler, Jörg | en_US |
| dc.contributor.author | Wald, Ingo | en_US |
| dc.contributor.author | Slusallek, Philipp | en_US |
| dc.contributor.editor | Thomas Ertl and Wolfgang Heidrich and Michael Doggett | en_US |
| dc.date.accessioned | 2013-10-28T10:00:19Z | |
| dc.date.available | 2013-10-28T10:00:19Z | |
| dc.date.issued | 2002 | en_US |
| dc.description.abstract | The ray tracing algorithm is well-known for its ability to generate high-quality images and its flexibility to support advanced rendering and lighting effects. Interactive ray tracing has been shown to work well on clusters of PCs and supercomputers but direct hardware support for ray tracing has been difficult to implement. In this paper, we present a new, scalable, modular, and highly efficient hardware architecture for real-time ray tracing. It achieves high performance with extremely low memory bandwidth requirements by efficiently tracing bundles of rays. The architecture is easily configurable to support a variety of workloads. For OpenGL-like scenes our architecture offers performance comparable to state-of-the-art rasterization chips. In addition, it supports all the usual ray tracing features including exact shadows, reflections, and refraction and is capable of efficiently handling complex scenes with millions of triangles. The architecture and its performance in different configurations is analyzed based on cycle-accurate simulations. | en_US |
| dc.description.seriesinformation | SIGGRAPH/Eurographics Workshop on Graphics Hardware | en_US |
| dc.identifier.isbn | 1-58113-580-1 | en_US |
| dc.identifier.issn | 1727-3471 | en_US |
| dc.identifier.uri | https://doi.org/10.2312/EGGH/EGGH02/027-036 | en_US |
| dc.publisher | The Eurographics Association | en_US |
| dc.subject | I.3.1 [Computer Graphics] | en_US |
| dc.subject | Hardware Architecture | en_US |
| dc.subject | I.3.7 [Computer Graphics] | en_US |
| dc.subject | Three Dimensional Graphics and Realism B.5.1 [Hardware Design] | en_US |
| dc.subject | Register | en_US |
| dc.subject | Transfer | en_US |
| dc.subject | Level Implementation | en_US |
| dc.title | SaarCOR - A Hardware Architecture for Ray Tracing | en_US |