An Architecture for High-Performance 2-D Image Display
| dc.contributor.author | Jordan, Stephen D. | en_US |
| dc.contributor.author | Jensen, Philip E. | en_US |
| dc.contributor.author | Lichtenbelt, Barthold B. A. | en_US |
| dc.contributor.editor | Bengt-Olaf Schneider and Andreas Schilling | en_US |
| dc.date.accessioned | 2014-02-06T14:33:56Z | |
| dc.date.available | 2014-02-06T14:33:56Z | |
| dc.date.issued | 1996 | en_US |
| dc.description.abstract | Image processing operations can be divided into two classes, those pre-processing operations that are market- and application-specific, and those widely-used operations that are useful in any application that requires the display of two-dimensional images. In the interest of achieving real-time rates for the broader class of 2-D image display operations, Hewlett-Packard has developed a hardware accel erator called VISUALIZE-IVX. It is capable of scaling, rotating, mirroring, translating and filtering lk-by-lk output images at greater than 30 frames/sec while simultaneously enhancing image brightness and contrast. This paper describes the pipelined architecture u.sed to'actiieve this performance oh a desktop computer. The Architecture makes use of a hybrid mapping scheme for geometric transformations. Also a unique memory device was designed that minimizes local image buffers while eliminating the need to resend pixels from main memory. A recently developed method of extending the filtering capabilities, that may be incorporated into future products, is also presented. | en_US |
| dc.description.seriesinformation | Eurographics Workshop on Graphics Hardware | en_US |
| dc.identifier.isbn | - | en_US |
| dc.identifier.issn | - | en_US |
| dc.identifier.uri | https://doi.org/10.2312/EGGH/EGGH96/039-045 | en_US |
| dc.publisher | The Eurographics Association | en_US |
| dc.title | An Architecture for High-Performance 2-D Image Display | en_US |
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