An Architecture for Ray - Bezier Patch Intersection

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dc.contributor.authorVijt, P Deen_US
dc.contributor.authorClaesen, Len_US
dc.contributor.authorMan, H Deen_US
dc.contributor.editorP. F. Lister and R. L. Grimsdaleen_US
dc.date.accessioned2014-02-06T14:24:18Z
dc.date.available2014-02-06T14:24:18Z
dc.date.issued1993en_US
dc.description.abstractA new fast ray - patch intersection algorithm is presented. The algorithm correctly handles all ray - patch intersections. A number of parametersare derived from a numerical analysis of the algorithm and the datapad is re synthesized for higher accuracy. A global architecture for anASIC for intersecting a ray with a bezier patch is presented. It is shownthat a cache combined with pre pads can reduce the required memory considerablewith an extremely small performance penalty. Attention will bepaid to the scheduling and control problem. Several high level optimizationsare presented that make efficient scheduling possible and decreasethe calculation time considerably.en_US
dc.description.seriesinformationEurographics Workshop on Graphics Hardwareen_US
dc.identifier.isbn-en_US
dc.identifier.issn-en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH93/093-112en_US
dc.publisherThe Eurographics Associationen_US
dc.titleAn Architecture for Ray - Bezier Patch Intersectionen_US
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EGGH93: Eurographics Workshop on Graphics Hardware 1993