Data-parallel Micropolygon Rasterization
| dc.contributor.author | Eisenacher, Christian | en_US |
| dc.contributor.author | Loop, Charles | en_US |
| dc.contributor.editor | H. P. A. Lensch and S. Seipel | en_US |
| dc.date.accessioned | 2015-07-09T10:00:39Z | |
| dc.date.available | 2015-07-09T10:00:39Z | |
| dc.date.issued | 2010 | en_US |
| dc.description.abstract | Abstract We implement a tile based sort-middle rasterizer in CUDA and study its performance characteristics when used as a backend for adaptive tessellation down to micropolygons. Tessellation and bucketing map very well to the data-parallel paradigm of CUDA, and the majority of time is spent with rasterization. Despite this, our fastest implementation is able to reach 30-50% of the hardware rasterization performance of an Nvidia GTX 280. Overall we are able to rasterize 4 M textured and Phong shaded microquads into a 1600x1200 framebuffer at 10-12 fps.Abstract We implement a tile based sort-middle rasterizer in CUDA and study its performance characteristics when used as a backend for adaptive tessellation down to micropolygons. Tessellation and bucketing map very well to the data-parallel paradigm of CUDA, and the majority of time is spent with rasterization. Despite this, our fastest implementation is able to reach 30-50% of the hardware rasterization performance of an Nvidia GTX 280. Overall we are able to rasterize 4 M textured and Phong shaded microquads into a 1600x1200 framebuffer at 10-12 fps. | en_US |
| dc.description.sectionheaders | Rendering | en_US |
| dc.description.seriesinformation | Eurographics 2010 - Short Papers | en_US |
| dc.identifier.doi | 10.2312/egsh.20101046 | en_US |
| dc.identifier.pages | 53-56 | en_US |
| dc.identifier.uri | https://doi.org/10.2312/egsh.20101046 | en_US |
| dc.publisher | The Eurographics Association | en_US |
| dc.title | Data-parallel Micropolygon Rasterization | en_US |