Codesign Of Graphics Hardware Accelerators

dc.contributor.authorEwins, Jon P.en_US
dc.contributor.authorL.Watten, Philen_US
dc.contributor.authorWhite, Martinen_US
dc.contributor.authorMcNeill, Michael D. J.en_US
dc.contributor.authorLister, Paul F.en_US
dc.contributor.editorA. Kaufmann and W. Strasser and S. Molnar and B.-O. Schneideren_US
dc.description.abstractThe design of a hardware architecture for a computer graphics pipeline requires a thorough understanding of the algorithms involved at each stage, and the implications these algorithms have on the organisation of the pipeline architecture. The choice of algorithm, the flow of pixel data through the pipeline, and bit width precision issues are crucial decisions in the design of new hardware accelerators. Making these decisions correctly requires intensive investigation and experimentation. The use of hardware description languages such as VHDL, allow for sound top down design methodologies, but their effectiveness in such experimental work is limited. This paper discusses the use of software tools as an aid to hardware development and presents applications that demonstrate the possibilities of this approach and the benefits that can be attained from an integrated codesign design environment.en_US
dc.description.seriesinformationSIGGRAPH/Eurographics Workshop on Graphics Hardwareen_US
dc.publisherThe Eurographics Associationen_US
dc.subjectD.3.2 [Programming Languages] Language Classificationsen_US
dc.subjectObject Oriented Programmingen_US
dc.subject1.3.1 [Computer Graphics]en_US
dc.subjectHardware Architectureen_US
dc.subjectGraphics Processorsen_US
dc.subject1.3.3 [Computer Graphics]en_US
dc.subjectPicture/Image Generationen_US
dc.subjectDisplay Algorithms.en_US
dc.titleCodesign Of Graphics Hardware Acceleratorsen_US
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