A PIPELINED-PARALLEL ARCHITECTURE FOR 2.5-D BATCH RASTERIZERS
| dc.contributor.author | Birk, Yitzhak | en_US |
| dc.contributor.author | Mccrossin, lames M . | en_US |
| dc.date.accessioned | 2015-10-05T07:56:29Z | |
| dc.date.available | 2015-10-05T07:56:29Z | |
| dc.date.issued | 1990 | en_US |
| dc.description.abstract | The emergence of application programs that take advantage of highly expressive page description languages has sharply increased the amount of computing required for rasterizing an average page, and single-microprocessor rasterizers presently limit the performance of most printers. The pipelined-parallel architecture employs intrapage parallelism to permit the construction of cost-effective multiprocessor rasterizers for computer-driven high-function printers. Initially, blocks of datastream that are independent in terms of datastream environment are identified by a sequential “scanner“. They are then processed in parallel, and each is converted into a multitude of simple, regular objects, which are sorted by “geographical” target on the page into “bins” that correspond to a predetermined partition of the page. Sequencing information is retained. The bins are then processed in parallel (sequentially within each bin) to build the full-page bitmap. The phases are pipelined for increased performance. By breaking rasterization into two main stages and parallelizing along a different dimension in each of them, we are able to attain intrapage parallelism while maintaining correctness, even with non commutative merging modes, such as “overpaint”. | en_US |
| dc.description.seriesinformation | EG 1990-Technical Papers | en_US |
| dc.identifier.doi | 10.2312/egtp.19901002 | en_US |
| dc.identifier.issn | 1017-4656 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.2312/egtp.19901002 | en_US |
| dc.publisher | Eurographics Association | en_US |
| dc.title | A PIPELINED-PARALLEL ARCHITECTURE FOR 2.5-D BATCH RASTERIZERS | en_US |