Latency- and Hazard-Free Volume Memory Ar­ chitecture for Direct Volume Rendering

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dc.contributor.authorBoer, M. deen_US
dc.contributor.authorGropl, A.en_US
dc.contributor.authorHesser, J.en_US
dc.contributor.authorMänner, R.en_US
dc.contributor.editorBengt-Olaf Schneider and Andreas Schillingen_US
dc.date.accessioned2014-02-06T14:33:58Z
dc.date.available2014-02-06T14:33:58Z
dc.date.issued1996en_US
dc.description.abstractThe computational power required for direct volume rendering like ray-casting or volume ray-tracing can be provided by high­ speed rendering architectures. However the increasing proces­ sor speed makes a performance bottleneck obvious - the vol­ ume memory. This paper describes a volume memory architec­ ture that achieves at least a tenfold speed-up in read-out rate with moderate additional hardware. It has been simulated suc­ cessfully. A multi-level cache system is used with software prefetching and latency hiding. Pre- and postcaches addi­ tionally speed up the read-out rate so that a 5123 data set stored in a single memory module can be rendered at 3.125 Hz.en_US
dc.description.seriesinformationEurographics Workshop on Graphics Hardwareen_US
dc.identifier.isbn-en_US
dc.identifier.issn-en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH96/109-119en_US
dc.publisherThe Eurographics Associationen_US
dc.titleLatency- and Hazard-Free Volume Memory Ar­ chitecture for Direct Volume Renderingen_US
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EGGH96: Eurographics Workshop on Graphics Hardware 1996