Graphics Algorithms on Field Programmable Function Arrays

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dc.contributor.authorSmit, Jaapen_US
dc.contributor.authorBosma, Marcoen_US
dc.contributor.editorBengt-Olaf Schneider and Andreas Schillingen_US
dc.date.accessioned2014-02-06T14:33:57Z
dc.date.available2014-02-06T14:33:57Z
dc.date.issued1996en_US
dc.description.abstractThe amount of energy consumed in basic CMOS building blocks, like external RAM, external bus-structures, multipliers, local (cache) memory and on chip bus-structures, is analyzed thoroughly to find ways for substantial improvement of the power consumption of high speed graphics algorithms: A Field Programmable Function Array capable of low-power execution of a wide range of algorithms is introduced. Aspects of the compilation of the volume rendering algorithm to this architecture are discussed.en_US
dc.description.seriesinformationEurographics Workshop on Graphics Hardwareen_US
dc.identifier.isbn-en_US
dc.identifier.issn-en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH96/103-108en_US
dc.publisherThe Eurographics Associationen_US
dc.titleGraphics Algorithms on Field Programmable Function Arraysen_US
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EGGH96: Eurographics Workshop on Graphics Hardware 1996