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    Timeline Scheduling for Out-of-Core Ray Batching

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    Date
    2017
    Author
    Son, Myungbae
    Yoon, Sung- Eui
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    Abstract
    We present a timeline based scheduling method for Monte Carlo ray tracing of out-of-core models on distributed memory clusters. We abstract different setups of various compute and memory devices into a graph-based representation, and estimate the time for job execution and data transfer in a simple timing model. Our scheduler allocates not only jobs to processors, but also data transfers to memory channels. This approach allows us to control the I/O overload, which is the principal bottleneck in rendering massivescale scenes. To manage dependencies of data transfers and data intensive jobs, each job and data transfer is arranged on the timeline with dependency relations. Based on this model, our scheduler aims to increase data locality by allocating a job that takes the least time to fetch required data on a given compute device. This goal is achieved by optimizing the data transfer path to maximize latency hiding effects. We have implemented a path tracer on our framework and tested massive models up to 500Mtriangles. Compared to prior state-of-the-art scheduling techniques, our renderer achieved higher horizontal scalability on flexible device configurations.
    BibTeX
    @inproceedings {10.1145:3105762.3105784,
    booktitle = {Eurographics/ ACM SIGGRAPH Symposium on High Performance Graphics},
    editor = {Vlastimil Havran and Karthik Vaiyanathan},
    title = {{Timeline Scheduling for Out-of-Core Ray Batching}},
    author = {Son, Myungbae and Yoon, Sung- Eui},
    year = {2017},
    publisher = {ACM},
    ISSN = {2079-8679},
    ISBN = {978-1-4503-5101-0},
    DOI = {10.1145/3105762.3105784}
    }
    URI
    http://dx.doi.org/10.1145/3105762.3105784
    https://diglib.eg.org:443/handle/10.1145/3105762-3105784
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    Eurographics Association copyright © 2013 - 2023 
    Send Feedback | Contact - Imprint | Data Privacy Policy | Disable Google Analytics
    Theme by @mire NV
    System hosted at  Graz University of Technology.
    TUGFhA