EG UK Theory and Practice of Computer Graphics 2009
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Browsing EG UK Theory and Practice of Computer Graphics 2009 by Subject "Categories and Subject Descriptors (according to ACM CCS): I.3.1 [Computer Graphics]: Graphics Processors"
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Item Design and Evaluation of a Hardware Accelerated Ray Tracing Data Structure(The Eurographics Association, 2009) Steffen, Michael; Zambreno, Joseph; Wen Tang and John CollomosseThe increase in graphics card performance and processor core count has allowed significant performance accel- eration for ray tracing applications. Future graphics architectures are expected to continue increasing the number of processor cores, further improving performance by exploiting data parallelism. However, current ray tracing implementations are based on recursive searches which involve multiple memory reads. Consequently, software implementations are used without any dedicated hardware acceleration. In this paper, we introduce a ray trac- ing method designed around hierarchical space subdivision schemes that reduces memory operations. In addition, parts of this traversal method can be performed in fixed hardware running in parallel with programmable graphics processors. We used a custom performance simulator that uses our traversal method, based on a kd-tree, to compare against a conventional kd-tree. The system memory requirements and system memory reads are analyzed in detail for both acceleration structures. We simulated six benchmark scenes and show a reduction in the number of memory reads of up to 70 percent compared to current recursive methods for scenes with over 100,000 polygons.Item Hardware Accelerated Shaders Using FPGAs(The Eurographics Association, 2009) Goddard, Luke; Stephenson, Ian; Wen Tang and John CollomosseWe demonstrate that Field Programable Gate Arrays (FPGAs) can be used to accelerate shading of surfaces for production quality rendering (a task standard interactive graphics hardware is generally ill-suited to) by allowing circuits to be dynamically created at run-time on standard commercial logic boards. By compiling shaders to hardware descriptions, they can be executed on FPGA with the performance of hardware without sacrificing the flexibility of software implementations. The resulting circuits are fully pipelined, and for circuits within the capacity of the FPGA can shade MicroPolygons at a fixed rate independent of shader complexity.