Design and Evaluation of a Hardware Accelerated Ray Tracing Data Structure

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dc.contributor.authorSteffen, Michaelen_US
dc.contributor.authorZambreno, Josephen_US
dc.contributor.editorWen Tang and John Collomosseen_US
dc.date.accessioned2014-01-31T20:06:43Z
dc.date.available2014-01-31T20:06:43Z
dc.date.issued2009en_US
dc.description.abstractThe increase in graphics card performance and processor core count has allowed significant performance accel- eration for ray tracing applications. Future graphics architectures are expected to continue increasing the number of processor cores, further improving performance by exploiting data parallelism. However, current ray tracing implementations are based on recursive searches which involve multiple memory reads. Consequently, software implementations are used without any dedicated hardware acceleration. In this paper, we introduce a ray trac- ing method designed around hierarchical space subdivision schemes that reduces memory operations. In addition, parts of this traversal method can be performed in fixed hardware running in parallel with programmable graphics processors. We used a custom performance simulator that uses our traversal method, based on a kd-tree, to compare against a conventional kd-tree. The system memory requirements and system memory reads are analyzed in detail for both acceleration structures. We simulated six benchmark scenes and show a reduction in the number of memory reads of up to 70 percent compared to current recursive methods for scenes with over 100,000 polygons.en_US
dc.description.seriesinformationTheory and Practice of Computer Graphicsen_US
dc.identifier.isbn978-3-905673-71-5en_US
dc.identifier.urihttp://dx.doi.org/10.2312/LocalChapterEvents/TPCG/TPCG09/101-108en_US
dc.publisherThe Eurographics Associationen_US
dc.subjectCategories and Subject Descriptors (according to ACM CCS): I.3.1 [Computer Graphics]: Graphics Processorsen_US
dc.titleDesign and Evaluation of a Hardware Accelerated Ray Tracing Data Structureen_US
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