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    Codesign Of Graphics Hardware Accelerators

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    103-109.pdf (813.3Kb)
    Date
    1997
    Author
    Ewins, Jon P.
    L.Watten, Phil
    White, Martin
    McNeill, Michael D. J.
    Lister, Paul F.
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    Abstract
    The design of a hardware architecture for a computer graphics pipeline requires a thorough understanding of the algorithms involved at each stage, and the implications these algorithms have on the organisation of the pipeline architecture. The choice of algorithm, the flow of pixel data through the pipeline, and bit width precision issues are crucial decisions in the design of new hardware accelerators. Making these decisions correctly requires intensive investigation and experimentation. The use of hardware description languages such as VHDL, allow for sound top down design methodologies, but their effectiveness in such experimental work is limited. This paper discusses the use of software tools as an aid to hardware development and presents applications that demonstrate the possibilities of this approach and the benefits that can be attained from an integrated codesign design environment.
    BibTeX
    @inproceedings {10.2312:EGGH:EGGH97:103-109,
    booktitle = {SIGGRAPH/Eurographics Workshop on Graphics Hardware},
    editor = {A. Kaufmann and W. Strasser and S. Molnar and B.-O. Schneider},
    title = {{Codesign Of Graphics Hardware Accelerators}},
    author = {Ewins, Jon P. and L.Watten, Phil and White, Martin and McNeill, Michael D. J. and Lister, Paul F.},
    year = {1997},
    publisher = {The Eurographics Association},
    ISSN = {1727-3471},
    ISBN = {0-89791-961-0},
    DOI = {10.2312/EGGH/EGGH97/103-109}
    }
    URI
    http://dx.doi.org/10.2312/EGGH/EGGH97/103-109
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    Eurographics Association copyright © 2013 - 2023 
    Send Feedback | Contact - Imprint | Data Privacy Policy | Disable Google Analytics
    Theme by @mire NV
    System hosted at  Graz University of Technology.
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