EGGH95: Eurographics Workshop on Graphics Hardware 1995

Permanent URI for this collection

https://diglib.eg.org/handle/10.2312/340

Single Chip Hardware Support for Rasterization and Texture Mapping

[meta data] [files:
015-024.pdf
]
Ackermann, Hans-Josef

The PixelFlow Texture and Image Subsystem

[meta data] [files:
003-013.pdf
]
Molnar, Steven

Hardware for Superior Texture Performance

[meta data] [files:
033-040.pdf
]
Knittel, G.
; 
Schilling, A.
; 
Kugler, A.
; 
Straßer, W.

Reducing Latency on PixelFlow

[meta data] [files:
043-049.pdf
]
Lastra, Anselmo A.

Approximation Techniques for High Performance Texture Mapping

[meta data] [files:
025-032.pdf
]
Demirer, Mehmet
; 
Grimsdale, Richard L.

An Architecture For Rapid Stereoscopic Image Generation

[meta data] [files:
057-062.pdf
]
MCCann, Shaun
; 
Lister, Paul

Design of an On-Chip Reflectance Map

[meta data] [files:
051-055.pdf
]
Scheltinga, Jeroen Terwisscha van
; 
Smit, Jaap
; 
Bosma, Marco

A pel-based Volume Rendering Accelerator

[meta data] [files:
073-082.pdf
]
Knittel, Günter

Hardware Supported Bump Mapping: A Step towards Ingber Quality Real-Time Rendering

[meta data] [files:
063-070.pdf
]
Emst, I.
; 
Jackel, D.
; 
Riisseler, H.
; 
Wittig, O.

Hardware Architecture for Voxelization-based Volume Rendering of Unstructured Grids

[meta data] [files:
103-115.pdf
]
Prakash, C. E.
; 
Manohar, S.

Super Resolution Volume Rendering Hardware

[meta data] [files:
117-122.pdf
]
Bosma, Marco
; 
Smit, Jaap
; 
Scheltinga, Jeroen Terwisscha van

Design of a Fast Voxel Processor for Parallel Volume Visualization

[meta data] [files:
083-092.pdf
]
Lichtennann, Jan

An array based design for Real-Time Volume Rendering

[meta data] [files:
093-101.pdf
]
Doggett, Michael

Towards a Scalable Architecture for Real-Time Volume Rendering

[meta data] [files:
123-130.pdf
]
Pfister, Hanspeter
; 
Kaufman, Arie
; 
Wessels, Frank

TENTH EUROGRAPHICS WORKSHOP ON GRAPHICS HARDWARE

[meta data] [files:
000_I+III_title.pdf ,
000_V+VI_contents.pdf
]
Straßer, Wolfgang

BibTeX (EGGH95: Eurographics Workshop on Graphics Hardware 1995)
@inproceedings{
:10.2312/EGGH/EGGH95/015-024,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
Single Chip Hardware Support for Rasterization and Texture Mapping}},

author = {
Ackermann, Hans-Josef
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/015-024}

}
@inproceedings{
:10.2312/EGGH/EGGH95/003-013,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
The PixelFlow Texture and Image Subsystem}},

author = {
Molnar, Steven
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/003-013}

}
@inproceedings{
:10.2312/EGGH/EGGH95/033-040,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
Hardware for Superior Texture Performance}},

author = {
Knittel, G.
 and 
Schilling, A.
 and 
Kugler, A.
 and 
Straßer, W.
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/033-040}

}
@inproceedings{
:10.2312/EGGH/EGGH95/043-049,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
Reducing Latency on PixelFlow}},

author = {
Lastra, Anselmo A.
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/043-049}

}
@inproceedings{
:10.2312/EGGH/EGGH95/025-032,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
Approximation Techniques for High Performance Texture Mapping}},

author = {
Demirer, Mehmet
 and 
Grimsdale, Richard L.
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/025-032}

}
@inproceedings{
:10.2312/EGGH/EGGH95/057-062,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
An Architecture For Rapid Stereoscopic Image Generation}},

author = {
MCCann, Shaun
 and 
Lister, Paul
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/057-062}

}
@inproceedings{
:10.2312/EGGH/EGGH95/051-055,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
Design of an On-Chip Reflectance Map}},

author = {
Scheltinga, Jeroen Terwisscha van
 and 
Smit, Jaap
 and 
Bosma, Marco
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/051-055}

}
@inproceedings{
:10.2312/EGGH/EGGH95/073-082,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
A pel-based Volume Rendering Accelerator}},

author = {
Knittel, Günter
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/073-082}

}
@inproceedings{
:10.2312/EGGH/EGGH95/063-070,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
Hardware Supported Bump Mapping: A Step towards Ingber Quality Real-Time Rendering}},

author = {
Emst, I.
 and 
Jackel, D.
 and 
Riisseler, H.
 and 
Wittig, O.
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/063-070}

}
@inproceedings{
:10.2312/EGGH/EGGH95/103-115,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
Hardware Architecture for Voxelization-based Volume Rendering of Unstructured Grids}},

author = {
Prakash, C. E.
 and 
Manohar, S.
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/103-115}

}
@inproceedings{
:10.2312/EGGH/EGGH95/117-122,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
Super Resolution Volume Rendering Hardware}},

author = {
Bosma, Marco
 and 
Smit, Jaap
 and 
Scheltinga, Jeroen Terwisscha van
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/117-122}

}
@inproceedings{
:10.2312/EGGH/EGGH95/083-092,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
Design of a Fast Voxel Processor for Parallel Volume Visualization}},

author = {
Lichtennann, Jan
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/083-092}

}
@inproceedings{
:10.2312/EGGH/EGGH95/093-101,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
An array based design for Real-Time Volume Rendering}},

author = {
Doggett, Michael
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/093-101}

}
@inproceedings{
:10.2312/EGGH/EGGH95/123-130,

booktitle = {
Tenth Eurographics Workshop on Graphics Hardware},

editor = {
W. Strasser
},
title = {{
Towards a Scalable Architecture for Real-Time Volume Rendering}},

author = {
Pfister, Hanspeter
 and 
Kaufman, Arie
 and 
Wessels, Frank
},
year = {
1995},

publisher = {
The Eurographics Association},


ISSN = {-},
ISBN = {-},

DOI = {
/10.2312/EGGH/EGGH95/123-130}

}

Browse

Recent Submissions

Now showing 1 - 15 of 15
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    Single Chip Hardware Support for Rasterization and Texture Mapping
    (The Eurographics Association, 1995) Ackermann, Hans-Josef; W. Strasser
    Today's interactive 3D-applications on Pes demand efficient hardware support for functionality, e.g. shading and texture mapping. In this paper, I present an ASIC that integrates most of the 3D-reIated functionality defined in Intel's de-facto standard 3DR. As the chip was designed for real time environmental simulation systems, the main focus has been on texture mapping, which provides the most natural appearance at a moderate effort level. To avoid artifacts during texture mapping, the chip performs bi- or tri-linear blending on a MIPmap structure. Texture addresses are calculated perspective correct. A crucial problem concerning the tri-linear blending is the necessary data bandwidth between ASIC and the texture buffer. Therefore, I discuss several memory types and architectures for the texture buffer depending on performance, price and board space requirements. A short overview of different system architectures using the ASIC concludes the paper.
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    The PixelFlow Texture and Image Subsystem
    (The Eurographics Association, 1995) Molnar, Steven; W. Strasser
    Texturing and imaging have become essential tasks for high­ speed, high-quality rendering systems. They make possible effects such as photo-textures, environment maps, decals, modulated transparency, shadows, environment maps, and bump maps, to name just a few.These operations all require high-speed access to a large "image" memory closely connected to the rasterizer hardware. The design of such memory systems is challenging because there are many competing constraints: memory bandwidth, memory size, flexibility, and, of course, cost PixelFlow is an experimental hardware architecture designed to support new levels of geometric complexity and to incorporate realistic rendering effects such as programmable shading. This required an extremely flexible and high-performance texture/image subsystem. This paper describes the PixelFlow texture/image subsystem, the design decisions behind it and its advantages and limitations. Future directions are also described.
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    Hardware for Superior Texture Performance
    (The Eurographics Association, 1995) Knittel, G.; Schilling, A.; Kugler, A.; Straßer, W.; W. Strasser
    Mapping textures onto suIfaces of computer-gener­ ated objects is a technique which greatly improves the realism of their appearance. Unfortunately, this imposes high computational demands and, even worse, tremendous memory bandwidth require­ ments on the graphics system. Tight cost frames in the industry in conjunction with ever increasing user expectations make the design of a powerful texture mapping unit a difficult task.To meet these requirements we follow two different approaches. On the technology side, we observe a rapidly emerging technology which offers the com­ bination of enormous transfer rates and computing power: logic-embedded memories.On the algorithmic side, a common way to reduce data traffic is image compression. Its application to texture mapping, however, is difficult since the decompression must be done at pixel frequency.In this work we will focus on the latter approach, describing the use of a specific compression scheme for texture mapping. It allows the use of a very sim­ ple and fast decompression hardware, bringing high performance texture mapping to low-cost systems.
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    Reducing Latency on PixelFlow
    (The Eurographics Association, 1995) Lastra, Anselmo A.; W. Strasser
    Performance, as measured by the number of primitives rendered per second, has been the most important rendering system design consideration while latency, the amount of time it takes to render an image, has largely been ignored. This is because a moderate amount of latency is not an issue for traditional interactive systems controlled by joysticks. However, latency has emerged as a major consideration when rendering for immersive systems, especially those using head-mounted displays. Maintaining low overall system latency is very important to create an illusion of presence in a virtual environment and very significant contribution to total system latency is the time it takes to generate an image. This paper examines some possible ways to reduce latency in the PixelFlow graphics computer.We first describe the standard rendering software for PixelFlow, and derive an expression for the time to render an image. We then propose two alternative software systems for the PixelFlow hardware. and derive expressions for the rendering latency. When we compare latencies for some common application scenarios, we find that the two prop~sed systems render with lower latency than the standard hlgh­ throughput system, but find that the benefits are not enough to outweigh the costs.
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    Approximation Techniques for High Performance Texture Mapping
    (The Eurographics Association, 1995) Demirer, Mehmet; Grimsdale, Richard L.; W. Strasser
    Accurate perspective mapping in real-time requires costly division operations per pixel and therefore ap­ proximation techniques are often employed. These per­ mit the mapping to be performed by interpolation, but generally with a significant set-up cost for the computa­ tion ofthe parameters. An efficient approximation tech­ nique which achieves good results with modest set-up requirements is presented. The technique uses Cheby­ shev control points to minimise errors.
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    An Architecture For Rapid Stereoscopic Image Generation
    (The Eurographics Association, 1995) MCCann, Shaun; Lister, Paul; W. Strasser
    A cost effective architecture for the rasterisation of stereo­ imagery based on image derivation is presented. The architecture is a simple and scaleable augmentation ofa classic monocular graphics pipeline and integrates stereoscopic photorealistic capability at comparatively little extra cost. Our architecture performs polygon derivation based on purely incremental operations and is well suited to implementation in hardware.
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    Design of an On-Chip Reflectance Map
    (The Eurographics Association, 1995) Scheltinga, Jeroen Terwisscha van; Smit, Jaap; Bosma, Marco; W. Strasser
    A reflectance map design is described which uses a minimal amount of memory for the table, in order to be applicable as an on-chip shader. The shader is designed for use with the volumetric super resolution hardware, which performs shading at supersampled locations. However, the design may be used as well to support surface visualization applications. Despite the small table size, the image quality obtained is excellent, even on smooth surfaces.
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    A pel-based Volume Rendering Accelerator
    (The Eurographics Association, 1995) Knittel, Günter; W. Strasser
    We discuss the underlying algorithms, design principles and implementation issues of an extremely compact and cost-efficient volume rendering accelerator for PCI-based systems. It operates on classified and shaded data sets which have been coded and compressed usingRedundant Block Compression (RBC), a tech­ nique originating from 2D-imaging and extended to 3D. This specific encoding scheme reduces drastically the required data traffic between the volume memory and the processing units. Thus, the volume data set can be placed into the main memory of the host, eliminating the need of a separate volume memory. Fur­ thermore, the tri-Iinear interpolation needed for perspective raycasting is very much simpli­ fied for RBC-transformed data sets.All in all, these techniques allow a volume ren­ dering accelerator to be implemented as a sin­ gle-chip coprocessor, or as an FPGA-based prototype for monochrome data sets as pre­ sented in this work. Although using a lossy compression scheme, image quality is still high, and expected frame rates are between 2 and 5Hz for typical data sets of 2563 voxels.
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    Hardware Supported Bump Mapping: A Step towards Ingber Quality Real-Time Rendering
    (The Eurographics Association, 1995) Emst, I.; Jackel, D.; Riisseler, H.; Wittig, O.; W. Strasser
    Today's high-end Gouraud renderers produce nicely textured scenes by mapping two-dimensional images onto modeled objects in real· time. We present a renderer which textures surfaces in the normal sense of the word using bump textures to simulate wrinkled or dimpled color­ ful surfaces. Using a simplified bump mapping method we first suc­ ceeded in designing a real-time bump mapping renderer based on the high-quality Phong shading model.Applying several improvements to our former Phong shading hard­ ware we are able to walk through perspectively correct bump mapped scenes illuminated by colored lightsources. This paper describes the main building blocks of the overall architec­ ture, including reflectance cubes to support a local viewer, a Taylor­ series based division to calculate homogeneous coordinates and our hardware adapted bump mapping method.
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    Hardware Architecture for Voxelization-based Volume Rendering of Unstructured Grids
    (The Eurographics Association, 1995) Prakash, C. E.; Manohar, S.; W. Strasser
    Interactive volume visualization of unstructured grid data is a much sought after, but as yet elusive, goal in many scientifie visualization applications. We present an architecture that ean possibly bring this goal within reach. In this architecture we combine the recently identified method of using texture mapping for volume rendering[5, 2] with anti-aliased voxelization. We show how the proposed architecture can be implemented with simple extensions to existing high-end graphics systems, using the SGI RealityEngine as an example. The ar­ ehitecture has the advantage of providing both direct volume rendering and polygon based rendering at high performance levels on the same hardware platform. We present some simulation results that demonstrate the validity of our architecture.
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    Super Resolution Volume Rendering Hardware
    (The Eurographics Association, 1995) Bosma, Marco; Smit, Jaap; Scheltinga, Jeroen Terwisscha van; W. Strasser
    The resolution obtained in volume rendering is greatly increased over known methods through the introduction of super resolution techniques which make it possible to enlarge the view o f the dataset without the introduction of unnecessary positional, gradient and opacity errors. In this paper our "Super Resolution" technique will be introduced along with a corresponding hardware design.
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    Design of a Fast Voxel Processor for Parallel Volume Visualization
    (The Eurographics Association, 1995) Lichtennann, Jan; W. Strasser
    The basics of a parallel real-time volume visualization architecture are introduced. Volume data is divided into subcubes that are dis­ tributed among multiple image processors and stored in their pri­ vate voxel memories. Rays fall into ray segments at the subcube borders. Each image processor is responsible for the ray segments within its assigned subcubes. Results of the ray segments are passed to the image processor where the ray continues. The enu­ meration of resampling points on the ray segments and the interpo­ lation at resampling points is accelerated by the voxel processor. The voxel processor can additionally compute a normalized gradi­ ent vector at a resampling point used as a surface normal estima­ tion for shading calculations. In the paper the focus is on operation and hardware implementation of this pipeline processor and the organization of voxel memory. The instruction set of the voxel pro­ cessor is explained. A performance of 20 images per second for a 2563 voxel volume and 16 image processors can be achieved.
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    An array based design for Real-Time Volume Rendering
    (The Eurographics Association, 1995) Doggett, Michael; W. Strasser
    This paper describes a new algorithm and hardware design for the generation of two dimensional images from volume data using the ray casting technique. The algorithm is part of an image generation system that is broken down into three subsystems. The first subsystem stores the input data in a buffered memory using a rearrangement of the original ad­ dress value. The second subsystem reads data points from the buffered memory and shifts the data to computational el­ ements in order to complete the viewing calculations for the image synthesis process. The final stage takes the results of the viewing calculations combined with the original input data to complete the surface rendering and pixel compositing to create the final image.This paper focusses on the second subsystem which con­ sists of two, two dimensional arrays of processing elements. The first array performs a limited angle, single dimension ro­ tation by shifting the data. The second array performs a two dimensional ray casting operation where viewing rays are as­ signed to each processing element. The first stage is outlined in this paper and the final rendering stages are the subject of previous work. The hardware design associated with these algorithms is described and tested. It is estimated that this ar­ chitecture is capable of producing 384 x 384 pixel images at speeds of 15 frames per second for 256 data sets. Real time generation of images of volume data is important in scientific applications of volume visualization and computer graphics applications which use volume graphics.
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    Towards a Scalable Architecture for Real-Time Volume Rendering
    (The Eurographics Association, 1995) Pfister, Hanspeter; Kaufman, Arie; Wessels, Frank; W. Strasser
    In this paper we present our research efforts towards a scalable volume rendering architecture for the real-time visualization of dynamically changing high-resolution datasets. Using a linearly skewed memory interleav­ ing we were able to develop a parallel dataflow model that leads to local, fixed-bandwidth interconnections be­ tween processing elements. This parallel dataflow model differs from previous work in that it requires no global communication of data except at the pixel level. Us­ ing this dataflow model we are developing Cube-4, an architecture that is scalable to very high performances and allows for modular and extensible hardware imple­ mentations.
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    TENTH EUROGRAPHICS WORKSHOP ON GRAPHICS HARDWARE
    (Eurographics Association, 1995-08-28) Straßer, Wolfgang
    Preface and Table of Contents