EGGH96: Eurographics Workshop on Graphics Hardware 1996

Eurographics DL Repository

EGGH96: Eurographics Workshop on Graphics Hardware 1996

 

Recent Submissions

  • Boer, M. de; Hesser, J.; Gropl, A.; Gunther, T.; Poliwoda, C.; Reinhart, C.; Manner, R. (The Eurographics Association, 1996)
    VIRIM, a real-time direct volume rendering system is evaluated for medical applications. Experiences concerning the hardware architecture are discussed. The issues are the flexibility of VIRIM, the restriction to two ...
  • Kanus, Urs; Meißner, Michael; Straßer, Wolfgang; Pfister, Hanspeter; Kaufman, Arie; Amerson, Rick; Carter, Richard J.; Culbertson, Bruce; Kuekes, Phil; Snider, Greg (The Eurographics Association, 1996)
    We present two implementations of the Cube-4 volume rendering architecture on the Teramac custom computing machine. Cube-4 uses a slice­ parallel ray-casting algorithm that allows for a paral­ lel and pipelined implementation ...
  • Boer, M. de; Gropl, A.; Hesser, J.; Männer, R. (The Eurographics Association, 1996)
    The computational power required for direct volume rendering like ray-casting or volume ray-tracing can be provided by high­ speed rendering architectures. However the increasing proces­ sor speed makes a performance ...
  • Smit, Jaap; Bosma, Marco (The Eurographics Association, 1996)
    The amount of energy consumed in basic CMOS building blocks, like external RAM, external bus-structures, multipliers, local (cache) memory and on chip bus-structures, is analyzed thoroughly to find ways for substantial ...
  • Leray, P. (The Eurographics Association, 1996)
    3D image analysis and automatic modelling using Neurofocalisation and attractiveness with hardwarefilters. Towards a new kind of filter-based data structures instead of splines/polygons.
  • Smit, J.; Bosma, M. (The Eurographics Association, 1996)
    A theory about the energy consumption of algorithms realized in CMOS, presented in related work, makes it possible to calculate the minimal amount of energy dissipated for the execution of an algorithm. The rendering of a ...
  • Banks, David C. (The Eurographics Association, 1996)
    Latency contributes to image error and to motion sickness in head­ tracked graphics displays. We attack the problem of latency by exploiting parallel scene generation, using multiple graphics engines to render images ...
  • McManus, Donald; Beckmann, Carl (The Eurographics Association, 1996)
    Designers of computer graphics hardware have used increasing device counts available from IC manufacturers to increase parallelism using techniques such as putting a longer pipeline of data path elements on integrated ...
  • Jordan, Stephen D.; Jensen, Philip E.; Lichtenbelt, Barthold B. A. (The Eurographics Association, 1996)
    Image processing operations can be divided into two classes, those pre-processing operations that are market- and application-specific, and those widely-used operations that are useful in any application that requires the ...
  • Kugler, Anders (The Eurographics Association, 1996)
    Integrating the slope and setup calculationsfor triangles to the rasterizer offloads the host processor from intensive calculations and can significantly increase 3D system performance. The processing on the host is greatly ...
  • Makris, "Alex; White, Martin; Lister", Paul (The Eurographics Association, 1996)
    This paper details the design o f an advanced 32 bit 3D frame buffer memory controller for a 3D Graphics Raster Processor called TAYRA [1]. This memory controller is designed to provide a performance o f 33 MPixelsls for ...
  • Waller, Marcus; Dunnett, Graham; Bassett, Mike; MCCann, Shaun; Makris, Alex; White, Martin; Lister, Paul (The Eurographics Association, 1996)
    This paper describes the Junctionality oj a 3D Graphics Raster Processor called TAYRA. TAYRA consists in the most part oj Graphics Raster Pipeline with five major external interfaces: PCI Master/Target, Depth, Texture, ...
  • Bennebroek, K.; Ernst, I.; Rüsseler, H.; Wittig, O. (The Eurographics Association, 1996)
    The VISA+ hardware architecture is the first of a new generation of graphics accelerators designed primarily to render bump-, texture-, environment- and environment-bump-mapped polygons. This paper presents examples of the ...