Lee, Jin-AeonKim, Lee-SupI. Buck and G. Humphreys and P. Hanrahan2013-10-282013-10-2820001-58113-257-31727-3471https://doi.org/10.2312/EGGH/EGGH00/067-076This paper describes a modified A-buffer algorithm and its hardware architecture for single-pass full-screen antialiasing. For storage and management of fragments, a dynamic memory management scheme, which can be efficiently implemented by hardware is introduced. In the fragment resolving stage, a subpixel color-blending scheme that resolves subpixels simultaneously is used to correctly blend transparencies and resolve intersections of polygons in a pixel. A rasterization processor architecture, which can process multiple pixels simultaneously, is also presented.I.3.3 [Computer Graphics]Picture/Image Generation AntialiasingI.3.1 [Computer Graphics]Hardware Architecture Graphics Processors