Smit, J.Bentum, M.Samsom, M.P. F. Lister and R. L. Grimsdale2014-02-062014-02-061993--https://doi.org/10.2312/EGGH/EGGH93/056-061The amount of power dissipated by the implementation of an algorithm, for instance in the form of a dedicatedchip-set, is considered to be one of the most important constraints for the selection of a high performance graphicsalgorithm. This is due to the fact that the realization of computational capability within the reach of one Teraoperations per second is non-practical with general purpose CPU-chips. The case study of a high performancesurface visualization engine is used to introduce the reader with the aspect of power dissipation in relation tocomputational power. We introduce a low-power' parallel datapath' RISe processor, based on a highly efficientmapping of locality of reference in the algorithm onto silicon. A subsequent classification is made for varioushigh performance graphics algorithms.