Jayasinghe, J.A.K.S.Herrmann, O.E.2015-10-052015-10-0519901017-4656https://doi.org/10.2312/egtp.19901000Generation of realistic images while supporting faster interaction is a topic in computer graphics research which has drawn considerable attention. Conventional frame buffer has been identified as a major bottle-neck for faster interaction [11]. Systolic Array Graphics (SAG) engines have been proposed to meet the above requirements by replacing the conventional frame buffer by a processor array. The speed limitations of the hardware restrict the use of SAG engines to displays resolutions of order 512x512 pixels when they are refreshed at 50Hz frame rate. In this paper we present an architectural solution to reduce the speed limitations of hardware. In the new architecture, a faster video stream is achieved by decoupling the speeds of the video and instruction streams by a multi-rate clocking scheme. We relax some timing constrains of the faster video stream by space domain multiplexing, i.e. using more wires.10.2312/egtp.19901000