Kugler, AHersch, R DP. F. Lister and R. L. Grimsdale2014-02-062014-02-061993--https://doi.org/10.2312/EGGH/EGGH93/113-118Halftoning is a fairly slow process when executedby software on conventional processors. To speed uphalf toning, a half toning algorithm has been developed andintegrated into a dedicated hardware architecture. Thispaper describes the implementation of the architecturewith a XILINX Field Programmable Gate Array (FPGA)and compares its performances with results obtained by asoftware implementation. A discussion on how to improvethe present architecture concludes the paper.