White, MDunnett, GLister, P FGrimsdale, RP. F. Lister and R. L. Grimsdale2014-02-062014-02-061993--https://doi.org/10.2312/EGGH/EGGH93/024-043The design of graphics ASICs for geometry and rasterisation processing has traditionally involved the use of schematic design entry where by functional blocks are netlisted and instantiatedon the schematic. This methodology is fine at the top most hierarchical levels ofa design but becomes tedious and error prone at the lower gate levels. Often these designsare targetted at custom ASICs through the use of silicon compiler technology. Unfortunately,this is an expensive and risky approach to implementing these ASICs, particularlyfor University research laboratories where additional funding may not be available to covernon-recurring engineering costs, such as multiple mask runs, which may be needed due to design errors. This paper presents an alternative to these traditional approachs. A new approach, top down ASIC design with logic synthesis and optimisation targetting FPGAASICs, is presented . We demonstrate through some examples of our texturing and scanconversion hardware the benefits of this new approach.