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Now showing 1 - 9 of 9
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    Polygon Rendering on a Stream Architecture
    (The Eurographics Association, 2000) Owens, John D.; Dally, William J.; Kapasi, Ujval J.; Rixner, Scott; Mattson, Peter; Mowery, Ben; I. Buck and G. Humphreys and P. Hanrahan
    The use of a programmable stream architecture in polygon rendering provides a powerful mechanism to address the high performance needs of today s complex scenes as well as the need for flexibility and programmability in the polygon rendering pipeline. We describe how a polygon rendering pipeline maps into data streams and kernels that operate on streams, and how this mapping is used to implement the polygon rendering pipeline on Imagine, a programmable stream processor. We compare our results on a cycleaccurate simulation of Imagine to representative hardware and software renderers.
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    Prefiltered Antialiased Lines Using Half-Plane Distance Functions
    (The Eurographics Association, 2000) McNamara, Robert; McCormack, Joel; Jouppi, Norman P.; I. Buck and G. Humphreys and P. Hanrahan
    We describe a method to compute high-quality antialiased lines by adding a modest amount of hardware to a fragment generator based upon half-plane edge functions. (A fragment contains the information needed to paint one pixel of a line or a polygon.) We surround an antialiased line with four edge functions to create a long, thin, rectangle. We scale the edge functions so that they compute signed distances from the four edges. At each fragment within the antialiased line, the four distances to the fragment are combined and the result indexes an intensity table. The table is computed by convolving a filter kernel with a prototypical line at various distances from the line s edge. Because the convolutions aren t performed in hardware, we can use wider, more complex filters with better high-frequency rejection than the narrow box filter common to supersampling antialiasing hardware. The result is smoother antialiased lines. Our algorithm is parameterized by the line width and filter radius. These parameters do not affect the rendering algorithm, but only the setup of the edge functions. Our algorithm antialiases line endpoints without special handling. We exploit this to paint small blurry squares as approximations to small antialiased round points. We do not need a different fragment generator for antialiased lines, and so can take advantage of all optimizations introduced in the existing fragment generator.
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    Towards Hardware Implementation Of Loop Subdivision
    (The Eurographics Association, 2000) Bischoff, Stephan; Kobbelt, Leif P.; Seidel, Hans-Peter; I. Buck and G. Humphreys and P. Hanrahan
    We present a novel algorithm to evaluate and render Loop subdivision surfaces. The algorithm exploits the fact that Loop subdivision surfaces are piecewise polynomial and uses the forward difference technique for efficiently computing uniform samples on the limit surface. The main advantage of our algorithm is that it only requires a small and constant amount of memory that does not depend on the subdivision depth. The simple structure of the algorithm enables a scalable degree of hardware implementation. By low-level parallelization of the computations, we can reduce the critical computation costs to a theoretical minimum of about one float[3]- operation per triangle.
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    Adaptive View Dependent Tessellation of Displacement Maps
    (The Eurographics Association, 2000) Doggett, Michael; Hirche, Johannes; I. Buck and G. Humphreys and P. Hanrahan
    Displacement Mapping is an effective technique for encoding the high levels of detail found in today s triangle based surface models. Extending the hardware rendering pipeline to be capable of handling displacement maps as geometric primitives, will allow highly detailed models to be constructed without requiring large numbers of triangles to be passed from the CPU to the graphics pipeline. We present a new approach based on recursive tessellation that adapts to the surface complexity described by the displacement map. We also ensure that the resolution of the displaced mesh is tessellated with respect to the current view point. Our tessellation scheme performs all tests only on triangle edges to avoid generating cracks on the displaced surface. The main decision for vertex insertion is based on two comparisons involving the average height surrounding the vertices and the normals at the vertices. Individually, the tests will fail to tessellate a mesh satisfactorily, but their combination achieves good results. We propose several additions to the typical hardware rendering pipeline in order to achieve displacement map rendering in hardware. The mesh tessellation is placed within the rendering pipeline so that we can take advantage of the pre-existing vertex transformation units to perform the setup calculations for our view dependent test. Our method adds only simple arithmetic and comparison operations to the graphics pipeline and makes use of existing units for calculations wherever possible.
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    Tiled Polygon Traversal Using Half-Plane Edge Functions
    (The Eurographics Association, 2000) McCormack, Joel; McNamara, Robert; I. Buck and G. Humphreys and P. Hanrahan
    Existing techniques for traversing a polygon generate fragments one (or more) rows or columns at a time. (A fragment is all the information needed to paint one pixel of the polygon.) This order is non-optimal for many operations. For example, most frame buffers are tiled into rectangular pages, and there is a cost associated with accessing a different page. Pixel processing is more efficient if all fragments of a polygon on one page are generated before any fragments on a different page. Similarly, texture caches have reduced miss rates if fragments are generated in tiles (and even tiles of tiles) whose size depends upon the cache organization. We describe a polygon traversal algorithm that generates fragments in a tiled fashion. That is, it generates all fragments of a polygon within a rectangle (tile) before generating any fragments in another rectangle. For a single level of tiling, our algorithm requires one additional saved context (the values of all interpolator accumulators, such as Z depth, Red, Green, Blue, etc.) over a traditional traversal algorithm based upon half-plane edge functions. An additional level of tiling requires another saved context for the special case of rectangle copies, or three more for the general case. We describe how to use this algorithm to generate fragments in an optimal order for several common scenarios.
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    Hardware-Accelerated Free-Form Deformation
    (The Eurographics Association, 2000) Chua, Clint; Neumann, Ulrich; I. Buck and G. Humphreys and P. Hanrahan
    Hardware-acceleration for geometric deformation is developed in the framework of an extension to the OpenGL specification. The method requires an addition to the front-end of the OpenGL rendering pipeline and an appropriate OpenGL primitive. Our approach is to implement general geometric deformations so the system supports additional layers of abstraction, including physically based simulations. This approach would support a wide range of users with an accelerated implementation of a wellunderstood deformation method, reducing the need for software deformation engines and the execution time penalty associated with them.
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    Single-Pass Full-Screen Hardware Accelerated Antialiasing
    (The Eurographics Association, 2000) Lee, Jin-Aeon; Kim, Lee-Sup; I. Buck and G. Humphreys and P. Hanrahan
    This paper describes a modified A-buffer algorithm and its hardware architecture for single-pass full-screen antialiasing. For storage and management of fragments, a dynamic memory management scheme, which can be efficiently implemented by hardware is introduced. In the fragment resolving stage, a subpixel color-blending scheme that resolves subpixels simultaneously is used to correctly blend transparencies and resolve intersections of polygons in a pixel. A rasterization processor architecture, which can process multiple pixels simultaneously, is also presented.
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    GI-Cube: An Architecture for Volumetric Global Illumination and Rendering
    (The Eurographics Association, 2000) Dachille, Frank; Kaufman, Arie; I. Buck and G. Humphreys and P. Hanrahan
    The power and utility of volume rendering is increased by global illumination. We present a hardware architecture, GI-Cube, designed to accelerate volume rendering, empower volumetric global illumination, and enable a host of ray-based volumetric processing. The algorithm reorders ray processing based on a partitioning of the volume. A cache enables efficient processing of coherent rays within a hardware pipeline. We study the flexibility and performance of this new architecture using both high and low level simulations.
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    Towards Interactive Bump Mapping with Anisotropic Shift-Variant BRDFs
    (The Eurographics Association, 2000) Kautz, Jan; Seidel, Hans-Peter; I. Buck and G. Humphreys and P. Hanrahan
    In this paper a technique is presented that combines interactive hardware accelerated bump mapping with shift-variant anisotropic reflectance models. An evolutionary path is shown how some simpler reflectance models can be rendered at interactive rates on current low-end graphics hardware, and how features from future graphics hardware can be exploited for more complex models. We show how our method can be applied to some well known reflectance models, namely the Banks model,Ward s model, and an anisotropic version of the Blinn-Phong model, but it is not limited to these models. Furthermore, we take a close look at the necessary capabilities of the graphics hardware, identify problems with current hardware, and discuss possible enhancements.