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Start date: 1980 × End date: 1989 × Subject: Raster Graphics ×

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Now showing 1 - 3 of 3
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    An Exact Incremental Hidden Surface RemovalAlgorithm
    (The Eurographics Association, 1987) Kuijk, A.A.M.; Hagen, P.J. W. ten; Akman, V.; Fons Kuijk and Wolfgang Strasser
    This paper describes an incremental Hidden Surface Removal Algorithm (HSRA), developed to be embedded in a new architecture for raster graphics described in [1,7]. The algorithm can be classified as "exact" since it operates in object space, rather than image space. It can be classified as "incremental" because this HSRA is able to support addition, removal and changes on a single object or a group of objects. Thus a firm basis for powerful interaction and animation is established. Due to specially designed data structures for both geometriC objects as well as storage of these objects, the hidden surface removal calculation on a complete scene will have the same time complexity as existing algorithms. However, the effort needed for incremental changes is much less than any other known algorithm. The data structures as well as the algorithm are designed to exploit parallelism in computation.
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    Two-level Pipelining of Systolic Array Graphics Engines
    (The Eurographics Association, 1989) Jayasinghe, J. A. K. S.; Herrmann, O. E.; Richard Grimsdale and Wolfgang Strasser
    In a systolic array, the maximum operating speed is determined by the most complex operation performed. In a systolic army graphics engine, capable of generating high quality images, one has to perform complex operations at a very high speed. We propose to use pipelined functional units in systolic army graphics engines as they can perform complex operations at high speeds. Due to time-varying discontinuities of operations performed by systolic army graphics engines, introduction of pipelined functional units is a complex problem. In this paper we present a methodology which solves this problem by a graph­ theoretic approach. Furthermore, we characterize the architectures which can be improved by pipelined functional units. Categories and Subject Descriptors: B.7.1 [Integrated Circuits}: Types and Design Styles VLSI C.l.1 [Single Data Stream Architectures}: Pipeline Processors C.S [Special-purpose and Application Based Systems}: Real-time Systems 1.3.1 [Computer Graphics]: Hardware Architecture - Raster Display Devices 1.3.7 [Computer Graphics]: Three-dimensional Graphics and Realism Color, Shading, Shadowing and Texture
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    Towards a Taxonomy for Display Processors
    (The Eurographics Association, 1989) Schneider, Bengt-Olaf; Richard Grimsdale and Wolfgang Strasser
    Image generation for raster displays proceeds in two main steps: geometry processing and pixel processing. The snbsystem performing the pixel processing is called display processor.In the paper a model for the displa.y processor is developed that takes into account both function and timing properties. The model identifies scan conversion, hidden surface removal, shading and anti-aliasing as tile key functions of the display processor. The timing model is expressed in an inequation being fundamental for all display processor architectures.On the basis of that model a taxonomy is presented which classifies display processors according to four main criteria: function, partitioning, a.rchitecture and performance.The taxonomy is applied to five real display processors: Pixel-planes, SLAM, PROOF, the Ray-Casting Machine and the Structured Frame Store System.Investigation of existing display processor architectures on the basis of the devel oped taxonomy revealed a potential new architecture. This architecture partitions the image generation process ill image space and employs a. tree topology.