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1987 - 19893
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Start date: 1980 × End date: 1989 × Subject: Algorithms ×

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Now showing 1 - 3 of 3
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    A Vector-like Architecture for Raster Graphics
    (The Eurographics Association, 1987) Akman, Varol; Hagen, Paul ten; Kuijk, Fons; Fons Kuijk and Wolfgang Strasser
    Raster graphics, while good at achieving realistic and cost-effective image generation, lacks useful (e.g. high-level) and fast (e.g. almost real-time) interaction facilities. One may try to speed up the entire classical image generation pipeline using much processing power but this would clearly lessen the advantages of raster workstations as popular, relatively inexpensive devices. This paper continues our work in restructuring the functional model (first formulated by Ingrid Carlbom) for high-performance architectures. Central to our approach is a visible concern about the underlying data structures used to represent the geometric objects. This originates from the conviction that only through careful design of appropriate graphics data structures and algorithms one can profitably map software tasks into hardware, specifically VLSI. Here we elaborate on a novel object description scheme called "pattern representation" and its envisioned usage. Our work is decidedly in contrast with several current research efforts in the area of graphics hardware where it is commonplace to simply put several processors into a cooperative effort to share the total burden, with each processor taking responsibility for part of the work.
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    Towards a Taxonomy for Display Processors
    (The Eurographics Association, 1989) Schneider, Bengt-Olaf; Richard Grimsdale and Wolfgang Strasser
    Image generation for raster displays proceeds in two main steps: geometry processing and pixel processing. The snbsystem performing the pixel processing is called display processor.In the paper a model for the displa.y processor is developed that takes into account both function and timing properties. The model identifies scan conversion, hidden surface removal, shading and anti-aliasing as tile key functions of the display processor. The timing model is expressed in an inequation being fundamental for all display processor architectures.On the basis of that model a taxonomy is presented which classifies display processors according to four main criteria: function, partitioning, a.rchitecture and performance.The taxonomy is applied to five real display processors: Pixel-planes, SLAM, PROOF, the Ray-Casting Machine and the Structured Frame Store System.Investigation of existing display processor architectures on the basis of the devel oped taxonomy revealed a potential new architecture. This architecture partitions the image generation process ill image space and employs a. tree topology.
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    Content-Addressable Memories for Quadtree-8ased Images
    (The Eurographics Association, 1988) Oldfield, J.V.; Williams, R.D.; Wiseman, N.E.; Brûlé, M.R.; A. A. M.Kuijk
    Quadtrees are attractive for storing and processing mages with area coherence, but performance has been limited by software overheads. A Content-Addressable Memory (CAM) with ternary storage allows single-cycle searches by pixel coordinate, quadrant or rectangle. To use thiS feature effectively the authors have reviewed a range of quadtree processing functions relevant to computer graphics and Image processing, and some new algorithms have been discovere. The proposed VLSI chip has microcoded logic on each row, as well as its CAM cells. This architecture has been simulated in fine detail with the aid of the Connection Machine as well as by much slower, conventional computers. The combination of quadtrees and CAMs offers significant improvement in performance for display systems and image processing.