Search Results

Now showing 1 - 10 of 47
  • Item
    Prefetching in a Texture Cache Architecture
    (The Eurographics Association, 1998) lgehy, Homan; Eldridge, Matthew; Proudfoot, Kekoa; S. N. Spencer
    Texture mapping has become so ubiquitous in real-time graphics hardware that many systems are able to perform filtered texturing without any penalty in fill rate. The computation rates available in hardware have been outpacing the memory access rates, and texture systems are becoming constrained by memory bandwidth and latency. Caching in conjunction with prefetching can be used to alleviate this problem. In this paper, WC introduce a prefetching texture cache architecture designed to take advantage of the access characteristics of texture mapping. The structures needed are relatively simple and arc amenable to high clock rates. To quantify the robustness of our architecture, we identify a set of six scenes whose texture locality varies over nearly two orders of magnitude and a set 01 four memory systems with varying bandwidths and latencies. Through the use of a cycle-accurate simulation, we demonstrate that even in the presence of a high-latency memory system, our architecture can attain at least 97% of the performance of a zerolatency memory system.
  • Item
    Design of a Fast Voxel Processor for Parallel Volume Visualization
    (The Eurographics Association, 1995) Lichtennann, Jan; W. Strasser
    The basics of a parallel real-time volume visualization architecture are introduced. Volume data is divided into subcubes that are dis­ tributed among multiple image processors and stored in their pri­ vate voxel memories. Rays fall into ray segments at the subcube borders. Each image processor is responsible for the ray segments within its assigned subcubes. Results of the ray segments are passed to the image processor where the ray continues. The enu­ meration of resampling points on the ray segments and the interpo­ lation at resampling points is accelerated by the voxel processor. The voxel processor can additionally compute a normalized gradi­ ent vector at a resampling point used as a surface normal estima­ tion for shading calculations. In the paper the focus is on operation and hardware implementation of this pipeline processor and the organization of voxel memory. The instruction set of the voxel pro­ cessor is explained. A performance of 20 images per second for a 2563 voxel volume and 16 image processors can be achieved.
  • Item
    VIZARD - Visualization Accelerator for Realtime Display
    (The Eurographics Association, 1997) Knittel, Günter; Straßer, Wolfgang; A. Kaufmann and W. Strasser and S. Molnar and B.-O. Schneider
    Volume rendering has traditionally been an application for supercomputers, workstation networks or expensive special-purpose hardware. In contrast, this report shows how far we have reached using the other extreme: the low-end PC platform. We have alleviated the mismatch between this demanding application and the limited computational resources of a PC in three ways: several stages in the visualization pipeline are placed into a preprocessing step, the volume rendering algorithm was optimized using a special data compression scheme, and the algorithm has been implemented in hardware as a PCI-compatible coprocessor (lXZ,4RD). These methods give us a frame rate of up to 1OHz for 256 <sup>3</sup> data sets and an acceptable image quality, although the accelerator prototype was built using relatively slow FPGA-technology. In a low-cost environment a coprocessor must not be more expensive than the host itself, and so VIZARD was designed to be manufacturable for a few hundred dollars. The special data compression scheme allows the data set to be placed into the main memory of the PC and eliminates the need for an expensive, separate volume memory. The entire visualization system consists of a portable PC with two built-in accelerator boards. Despite its small size, the system provides perspective raycasting for realtime walk-throughs. Additional features include stereoscopic viewing using shutter glasses and volume animation.
  • Item
    An Improved Z-Buffer CSG Rendering Algorithm
    (The Eurographics Association, 1998) Stewart, Nigel; Leach, Geoff; John, Sabu; S. N. Spencer
    We present an improved z-buffer based CSG rendering algorithm, based on previous techniques using z-buffer parity based surface clipping. We show that while this type of algorithm has been reported as requiring O(n2), (where n is the number of primitives), an O(lcn) (where k is depth complexity) algorithm may be substituted. For cases where k is less than n this translates into a significant performance gain.
  • Item
    Real-Time Bump Map Synthesis
    (The Eurographics Association, 2001) Kautz, Jan; Heidrich, Wolfgang; Seidel, Hans-Peter; Kurt Akeley and Ulrich Neumann
    In this paper we present a method that automatically synthesizes bump maps at arbitrary levels of detail in real-time. The only input data we require is a normal density function; the bump map is generated according to that function. It is also used to shade the generated bump map. The technique allows to infinitely zoom into the surface, because more (consistent) detail can be created on the fly. The shading of such a surface is consistent when displayed at different distances to the viewer (assuming that the surface structure is self-similar). The bump map generation and the shading algorithm can also be used separately.
  • Item
    Point-driven Generation of Images from a Hierarchical Data Structure
    (The Eurographics Association, 1988) Jong, Dirk de; Siobbe, Paul van; Splunter, Marinus van; A. A. M.Kuijk
    In this paper, a system IS described which renders an image from a hierarchical data structure in a point-driven way. The data structure allows dynamic color mapping and arbitrary affine transformat·ons of objects with respect to their parent coordinate system. The point driven method allows for easy VLSI implementation, efficient use oj memory and exploitation of parallelism.
  • Item
    Parallel Texture Caching
    (The Eurographics Association, 1999) lgehy, Homan; Eldridge, Matthew; Hanrahan, Pat; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
    The creation of high-quality images requires new functionality and higher performance in real-time graphics architectures. In terms of functionality, texture mapping has become an integral component of graphics systems, and in terms of performance, parallel techniques are used at all stages of the graphics pipeline. In rasterization, texture caching has become prevalent for reducing texture bandwidth requirements. However, parallel rasterization architectures divide work across multiple functional units, thus potentially decreasing the locality of texture references. For such architectures to scale well, it is necessary to develop efficient parallel texture caching subsystems. We quantify the effects of parallel rasterization on texture locality for a number of rasterization architectures, representing both current commercial products and proposed future architectures. A cycle-accurate simulation of the rasterization system demonstrates the parallel speedup obtained by these systems and quantities inefficiencies due to redundant work, inherent parallel load imbalance, insufftcient memory bandwidth, and resource contention. We find that parallel texture caching works well, and is general enough to work with a wide variety of rasterization architectures.
  • Item
    VoxelCache: A Cache-Based Memory Architecture for Volume Graphics
    (The Eurographics Association, 2003) Kanus, U.; Wetekam, G.; Hirche, J.; M. Doggett and W. Heidrich and W. Mark and A. Schilling
    This paper presents a cache-based memory architecture for volume graphics. We describe the memory organization and cache logic to implement a voxel cache based on 43 voxel blocks. We show an efficient prefetching scheme that increases the cache hit ratio to more than 98% in most cases. The performance of the memory system with different types of external memory is demonstrated by a cycle accurate C++ simulation. The VoxelCache memory architecture is designed to be easily adapted to different memory technologies, because all volume graphics specific parts of the memory system are encapsulated inside the on-chip cache. The design is targeted at implementation on off-the-shelf reconfigurable hardware.
  • Item
    Memory Access Patterns of Occlusion-Compatible 3D Image Warping
    (The Eurographics Association, 1997) Murk, William R.; Bishop, Gary; A. Kaufmann and W. Strasser and S. Molnar and B.-O. Schneider
    McMillan and Bishop s 3D image warp can be efficiently implemented by exploiting the coherency of its memory accesses. We analyze this coherency, and present algorithms that take advantage of it. These algorithms traverse the reference image in an occlusion-compatible order, which is an order that can resolve visibility using a painter s algorithm. Required cache sizes are calculated for several one-pass 3D warp algorithms, and we develop a two-pass algorithm which requires a smaller cache size than any of the practical one-pass algorithms. We also show that reference image traversal orders that are occlusion-compatible for continuous images are not always occlusion-compatible when applied to the discrete images used in practice.
  • Item
    Z3: An Economical Hardware Technique for High-Quality Antialiasing and Transparency
    (The Eurographics Association, 1999) Jouppi, Norman P.; Chang, Chun-Fa; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
    In this paper we present an algorithm for low-cost hardware antialiasing and transparency. This technique keeps a central Z value along with compact floating-point Z gradients in the X and Y dimensions for each fragment within a pixel (hence the name Z3). It uses a small fixed amount of storage per pixel. If the visible complexity of the pixel exceeds the storage space available for the pixel, the minimum number of fragments having the closest Z values are merged. This combines different fragments from the same surface, resulting in both storage and processing efficiency. When operating with opaque surfaces, Z3 can provide superior image quality over sparse supersampling methods that use eight samples per pixel while using storage for only three fragments. Z3 also makes the use of large numbers of samples (e.g., 16) feasible in inexpensive hardware, enabling higher quality images. It is simple to implement because it uses a small fixed number of fragments per pixel. Z3 can also provide order-independent transparency even if many transparent surfaces are present. Moreover, unlike the original A-buffer algorithm it correctly antialiases interpenetrating transparent surfaces because it has three-dimensional Z information within each pixel.