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Now showing 1 - 10 of 11
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    A Virtual Memory System Organization for Bit-Mapped Graphics Displays
    (The Eurographics Association, 1989) Barkans, Anthony C.; Richard Grimsdale and Wolfgang Strasser
    Described is a display sub-system, designed for support of a very high speed rendering engine. It provides high-performance graphics to an enVironment that consists of a hierarchy of resizable windows. The concept of virtual memory has been applied with the organization of the virtual to physical address spaces having a unique mapping that fits the organization of a bit-mapped graphics memory display.
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    Point-driven Generation of Images from a Hierarchical Data Structure
    (The Eurographics Association, 1988) Jong, Dirk de; Siobbe, Paul van; Splunter, Marinus van; A. A. M.Kuijk
    In this paper, a system IS described which renders an image from a hierarchical data structure in a point-driven way. The data structure allows dynamic color mapping and arbitrary affine transformat·ons of objects with respect to their parent coordinate system. The point driven method allows for easy VLSI implementation, efficient use oj memory and exploitation of parallelism.
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    Memory Access Patterns of Occlusion-Compatible 3D Image Warping
    (The Eurographics Association, 1997) Murk, William R.; Bishop, Gary; A. Kaufmann and W. Strasser and S. Molnar and B.-O. Schneider
    McMillan and Bishop s 3D image warp can be efficiently implemented by exploiting the coherency of its memory accesses. We analyze this coherency, and present algorithms that take advantage of it. These algorithms traverse the reference image in an occlusion-compatible order, which is an order that can resolve visibility using a painter s algorithm. Required cache sizes are calculated for several one-pass 3D warp algorithms, and we develop a two-pass algorithm which requires a smaller cache size than any of the practical one-pass algorithms. We also show that reference image traversal orders that are occlusion-compatible for continuous images are not always occlusion-compatible when applied to the discrete images used in practice.
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    PixelFlow: The Realization
    (The Eurographics Association, 1997) Eyles, John; Molnar, Steven; Poulton, John; Greer, Trey; Lastra, Anselmo; England, Nick; Westover, Lee; A. Kaufmann and W. Strasser and S. Molnar and B.-O. Schneider
    PixelFlow is an architecture for high-speed, highly realistic image generation, based on the techniques of object-parallelism and image composition. Its initial architecture was described in [MOLN92]. After development by the original team of researchers at the University of North Carolina, and codevelopment with industry partners, Division Ltd. and Hewlett- Packard, PixelFlow now is a much more capable system than initially conceived and its hardware and software systems have evolved considerably. This paper describes the final realization of PixelFlow, along with hardware and software enhancements heretofore unpublished.
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    Quadratic Bezier Triangles As Drawing Primitives
    (The Eurographics Association, 1998) Bruijns, J.; S. N. Spencer
    We propose to use quadratic Bezier triangles as additional drawing primitives: quadratic Bezier triangles require much less model data for faithful representation of curved surfaces than planar triangles. Therefore, they require less storage and/or transmission capacity. Furthermore, they allow automatic level-of-detail. Finally, they result in considerable savings in model-view transformations and lighting calculations. We present two algorithms for rendering these triangles, each of which can be easily incorporated in hardware render systems currently used for planar triangles.
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    Neon: A Single-Chip 3D Workstation Graphics Accelerator
    (The Eurographics Association, 1998) McCormack, Joel; McNamara, Robert; Gianos, Christopher; Seiler, Larry; Jouppi, Norman P.; Correll, Ken; S. N. Spencer
    High-performance 3D graphics accelerators traditionally require multiple chips on multiple boards, including geometry, rasterizing, pixel processing, and texture mapping chips. These designs are often scalable: they can increase performance by using more chips. Scalability has obvious costs: a minimal configuration needs several chips, and some configurations must replicate texture maps. A less obvious cost is the almost irresistible temptation to replicate chips to increase performance, rather than to design individual chips for higher performance in the first place. In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL [19] 3D rendering, as well as X11 [20] and Windows/NT 2D rendering. Since our pin budget limited peak memory bandwidth, we designed Neon from the memory system upward in order to reduce bandwidth requirements. Neon has no special-purpose memories; its eight independent 32-bit memory controllers can access color buffers, 1. depth buffers, stencil buffers, and texture data. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital s Alpha CPUs. Neon s performance is between HP s Visualize fx<sup>4</sup> and fx<sup>6</sup>, and is well above SGI s MXE for most operations. Neon-based boards cost much less than these competitors, due to a small part count and use of commodity SDRAMs.
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    Codesign Of Graphics Hardware Accelerators
    (The Eurographics Association, 1997) Ewins, Jon P.; L.Watten, Phil; White, Martin; McNeill, Michael D. J.; Lister, Paul F.; A. Kaufmann and W. Strasser and S. Molnar and B.-O. Schneider
    The design of a hardware architecture for a computer graphics pipeline requires a thorough understanding of the algorithms involved at each stage, and the implications these algorithms have on the organisation of the pipeline architecture. The choice of algorithm, the flow of pixel data through the pipeline, and bit width precision issues are crucial decisions in the design of new hardware accelerators. Making these decisions correctly requires intensive investigation and experimentation. The use of hardware description languages such as VHDL, allow for sound top down design methodologies, but their effectiveness in such experimental work is limited. This paper discusses the use of software tools as an aid to hardware development and presents applications that demonstrate the possibilities of this approach and the benefits that can be attained from an integrated codesign design environment.
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    High-Quality Volume Rendering Using Texture Mapping Hardware
    (The Eurographics Association, 1998) Dachille, Frank; Kreeger, Kevin; Chen, Baoquan; Bitter, Ingmar; Kaufman, Arie; S. N. Spencer
    We present a method Jor volume rendering of regular grids which takes advantage of 3D texture mapping hardware currently, available on graphics workstations. Our method products accurate shading for arbitrary and dynamically changing directional lights, viewing parameters, and transfer functions. This is achieved by hardware interpolating the data values and gradients before software classification and shading. The method works equally well for parallel and perspective projections. We present two approaches for OUT method: one which takes advantage of software ray casting optimizations and another which takes advantage of hardware blending acceleration.
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    View-independent Environment Maps
    (The Eurographics Association, 1998) Heidrich, Wolfgang; Seidel, Hans-Peter; S. N. Spencer
    Environment maps are widely used for approximating reflections in hardware-accelerated rendering applications. Unfortunately, the parameterizations for environment maps used in today s graphics hardware severely undersample certain directions, and can thus not be used from multiple viewing directions. Other parameterizations exist, but require operations that would be too expensive for hardware implementations. In this paper we introduce an inexpensive new parameterization for environment maps that allows us to reuse the environment map for any given viewing direction. We describe how, under certain restrictions, these maps can be used today in standard OpenGL implementations. Furthermore, we explore how OpenGL could be extended to support this kind of environment map more directly.
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    IMEM: An Intelligent Memory for Bump- and Reflection-Mapping
    (The Eurographics Association, 1998) Kugler, Anders; S. N. Spencer
    Data path simplification in the context of reflection- and bumpmapping hardware opens new solutions in the design of rendering and shading circuits. We are proposing a novel approach to rendering bump- and reflection-mapped surfaces, where the local geometry defining bump-maps is transformed on-the-fly prior to surface shading. Applying angular encoding to normal vectors results in narrower data paths and permits hardware integration of look-up tables of acceptable size. A special-purpose logic-embedded memory architecture is presented, where bump- and reflection-mapping of textured surfaces are executed by an intelligent memory device. High-performance surface shading is achieved by making use of precomputed shading- and reflection-map coordinate generation tables, and considering cache coherence of pixel-to-pixel normal vectors. Such a dedicated memory chip can easily be interfaced to a standard rasterizer, in place of texture memory to offer bump-, texture- and reflection-mapping hardware support.