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Now showing 1 - 5 of 5
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    Incremental and Hierarchical Hilbert Order Edge Equation Polygon Rasterization
    (The Eurographics Association, 2001) McCool, Michael D.; Wales, Cluis; Moule, Kevin; Kurt Akeley and Ulrich Neumann
    A rasterization algorithm must efficiently generate pixel fragments from geometric descriptions of primitives. ln order to accomplish per-pixel shading, shading parameters must also be interpolated across the primitive in a perspective-correct manner. lf some of these parameters are to be interpreted in later stages of the pipeline directly or indirectly as texture coordinates, then translating spatial and parametric coherence into temporal coherence will improve texture cache performance. Finally, if framebuffer access is also organized around cached blocks, then organizing rasterization so fragments are generated in block-sequential order will maximize framebuffer cache performance. Hilbert-order rasterization accomplishes these goals, and also permits efficient incrementale valuation of edge and interpolation equations.
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    Vertex-based Anisotropic Texturing
    (The Eurographics Association, 2001) Olano, Marc; Mukherjee, Shrijeet; Dorbie, Angus; Kurt Akeley and Ulrich Neumann
    MIP mapping is a common method used by graphics hardware to avoid texture aliasing. In many situations, MIP mapping over-blurs in one direction to prevent aliasing in another. Anisotropic texturing reduces this blurring by allowing differing degrees of filtering in different directions, but is not as common in hardware due to the implementation complexity of current techniques. We present a new algorithm that enables anisotropic texturing on any current MIP map graphics hardware supporting MIP level biasing, available in OpenGL 7.2 or through the GLEXT-texture-lod-bias or GL-SGIX-texture-lod-bias OpenGL extensions. The new algorithm computes anisotropic filter footprint parameters per vertex. It constructs the anisotropic filter out of several MIP map texturing passes or multitexture lookups. Each lookup uses MIP level bias and perturbed texture coordinates to place one probe used to construct the more complex filter profile.
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    Perlin Noise Pixel Shaders
    (The Eurographics Association, 2001) Hart, John C.; Kurt Akeley and Ulrich Neumann
    While working on a method for supporting real-time procedural solid texturing, we developed a general purpose multipass pixel shader to generate the Perlin noise function. We implemented this algorithm on SGI workstations using accelerated OpenGL PixelMap and PixelTransfer operations, achieving a rate of 2.5 Hz for a 256x256 image. We also implemented the noise algorithm on the NVidia GeForce2 using register combiners. Our register combiner implementation required 375 passes, but ran at 1.3 Hz. This exercise illustrated a variety of abilities and shortcomings of current graphics hardware. The paper concludes with an exploration of directions for expanding pixel shading hardware to further support iterative multipass pixel-shader applications.
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    The F-Buffer: A Rasterization-Order FIFO Buffer for Multi-Pass Rendering
    (The Eurographics Association, 2001) Mark, William R.; Proudfoot, Kekoa; Kurt Akeley and Ulrich Neumann
    Multi-pass rendering is a common method of virtualizing graphics hardware to overcome limited resources. Most current multi-pass rendering techniques use the RGBA framebuffer to store intermediate results between each pass. This method of storing intermediate results makes it difficult to conectly render partially-transparent surfaces, and reduces the performance of shaders that need to preserve more than one intermediate result between passes. We propose an alternative approach to storing intermediate results that solves these problems. This approach stores intermediate colors (or other values) that are generated by a rendering pass in a FIFO buffer as the values exit the fragment pipeline. On a subsequent pass, the contents of the FIFO buffer are fed into the top of the fragment pipeline. We refer to this FIFO buffer as a fragment-stream buffer (or F-buffer), because this approach has the effect of associating intermediate results with particular rasterization fragments, rather than with an (x,y) location in the framebuffer. Implementing an F-buffer requires some changes to current mainstream graphics architectures, but these changes can be minor. We describe the designs pace associated with implementing an F-buffer, and compare the F-buffer to recirculating pipeline designs. We implement F-buffers in the Mesa software renderer, and demonstrate our programmable-shading system running on top of this renderer.
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    Compiling to a VLIW Fragment Pipeline
    (The Eurographics Association, 2001) Mark, William R.; Proudfoot, Kekoa; Kurt Akeley and Ulrich Neumann
    The latest generation of graphics hardware supports fully programmable vertex and pixel/fragment operations, but programming this hardware at a low level is difficult and time consuming. To address this problem, we have developed a complete real-time procedural shading system that compiles a high-level shading language to programmable vertex and fragment hardware, as described in a separate publication. In this paper, we describe in detail the algorithms used by this system to generate and optimize fragment code for NVIDIAs register combiner architecture and show that our compiler generates efficient code. The register combiner architecture has some similarities to WIW CPU architectures, so we compare our compilation algorithms to those described in the literature for VLIW CPU architectures. We also discuss some of the lessons we leamed from building and using this compiler that may be useful to the designers of future programmable graphics hardware.