Browsing EGGH96: Eurographics Workshop on Graphics Hardware 1996 by Title

Now showing items 10-13 of 13

    • On the energy complexity of Algorithms realized in CMOS, a Graphics Example 

      Smit, J.; Bosma, M. (The Eurographics Association, 1996)
      A theory about the energy consumption of algorithms realized in CMOS, presented in related work, makes it possible to calculate the minimal amount of energy dissipated for the execution of an algorithm. The rendering of a ...

    • Optimal Static 2-Dimensional Screen Subdivision for Parallel Rasterization Architectures 

      McManus, Donald; Beckmann, Carl (The Eurographics Association, 1996)
      Designers of computer graphics hardware have used increasing device counts available from IC manufacturers to increase parallelism using techniques such as putting a longer pipeline of data path elements on integrated ...

    • The Setup for Triangle Rasterization 

      Kugler, Anders (The Eurographics Association, 1996)
      Integrating the slope and setup calculationsfor triangles to the rasterizer offloads the host processor from intensive calculations and can significantly increase 3D system performance. The processing on the host is greatly ...

    • TAYRA - A 3D Graphics Raster Processor 

      Waller, Marcus; Dunnett, Graham; Bassett, Mike; MCCann, Shaun; Makris, Alex; White, Martin; Lister, Paul (The Eurographics Association, 1996)
      This paper describes the Junctionality oj a 3D Graphics Raster Processor called TAYRA. TAYRA consists in the most part oj Graphics Raster Pipeline with five major external interfaces: PCI Master/Target, Depth, Texture, ...