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A Two-Dimensional Frame Buffer Processor
(The Eurographics Association, 1987)
The two-dimensional Frame Buffer Processor (FBP) is part of a proposed raster graphics computer architecture. It is a hardware-oriented organisation of a variation of a bitblt engine with a much richer repertoire. In ...
AVLSI Chip for Ray Tracing Bicubic Patches
(The Eurographics Association, 1986)
A VLSI chip for ray tracing bicubic patches in Bezier form is explored. The purpose of the chip is to calculate the intersection point of a ray with the bicubic patch to a specified level of accuracy, returning the location ...
VLSI Architecture for Anti-Aliasing
(The Eurographics Association, 1989)
Computer-synthesized images exhibit the typical artifacts of raster displays, called alias ing, rastering, staircasing or the "jaggies". Display of an image on a raster CRT requires the sampling the two dimensional image ...
Two-level Pipelining of Systolic Array Graphics Engines
(The Eurographics Association, 1989)
In a systolic array, the maximum operating speed is determined by the most complex operation performed. In a systolic army graphics engine, capable of generating high quality images, one has to perform complex operations ...
The voxblt Engine: A Voxel Frame Buffer Processor
(The Eurographics Association, 1988)
The voxblt Engine (vE) is a 3D frame-buffer processor which manipulates and processes ''3~ bitmaps"" (voxel maps) stored in a cubic frame buffer of voxels. The vE is the 3D counterpart of the 20 frame buffer processor, ...
A Survey of Simulator Requirements
(The Eurographics Association, 1986)
Simulators have been developed to train pilots, sailors or car drivers withoutthe costs and risks of moving their real vehicles. To obtain high success intraining, the simulators have to provide a high level of realism. ...
Content-Addressable Memories for Quadtree-8ased Images
(The Eurographics Association, 1988)
Quadtrees are attractive for storing and processing mages with area coherence, but performance has been limited by software overheads. A Content-Addressable Memory (CAM) with ternary storage allows single-cycle searches ...
A VLSI Architecture for Image Composition
(The Eurographics Association, 1988)
This paper describes a new parallel architecture for performing high-speed raster graphics. A central host broadcasts graphical objects to a number of identical graphics processors. Each graphics processor produces a raster ...
Hardware Support for the Display and Manipulation of Binary Voxel Models
(The Eurographics Association, 1988)
We describe some of our experiences with the implementation of a 3D reconstruction system for the visualization of the shapes and structural development of biological objects. We use a binary voxel model as volumetric ...
Parallel Processing on a Transputer-based Graphics Board
(The Eurographics Association, 1988)
Th.s paper discusses the design of a graphics board with parallel architecture based on Transputers and a resolution of 1024 x 1024 x 8 [VIN88], namely: Ihe processing unit (il plays the role of a display processor), the ...