EGGH92: Eurographics Workshop on Graphics Hardware 1992
https://diglib.eg.org:443/handle/10.2312/343
ISBN2024-03-29T04:51:01ZHidden contours on a frame-buffer
https://diglib.eg.org:443/handle/10.2312/EGGH.EGGH92.188-203
Hidden contours on a frame-buffer
Rossignac, Jarek R.; Emmerik, Maarten van
P F Lister
To comply with drafting practices and because shaded images do not always reveal the internal or hiddenstructures of 3D models, designers need wireframe images with hidden lines dashed and nonconlour tesselation edges removed. Software techniques for wireframe rendering of polyhedra that require the viewpoint-dependent identilication of the visible portions of intersection and contour (i.e. silhouette)edges are too slow for interactive applications. Hardware support in contemporary graphics pipelines is unavailable or at best limited to the identification of contour edges. In this paper, new hardware assisted techniques for hidden-line removal and determination of contour edges are presented. The techniques do not require any face/edge adjacency information and can be implemented easily on any platform that supports a hardware z-buffer.
1992-01-01T00:00:00ZAn Efficient Massively Parallel Rasterization Scheme For a High Performance Graphics System
https://diglib.eg.org:443/handle/10.2312/EGGH.EGGH92.158-169
An Efficient Massively Parallel Rasterization Scheme For a High Performance Graphics System
Karpf, S.; Chaillou, C.
P F Lister
We present in this paper the IMOGENE II system, a massively parallelMulti-SIMD graphics system. This architecture uses a new rasterization scheme combining Object Parallelism and Parallel Virtual Buffers. This scheme leads to a better efficiency than other massively parallel SHvlD systems, and allows a cost-effective, powerful and easily expandable system to be designed. The system consists of several SIMD ScanConversionPipelines each connected to a Multi-Level Virtual Buffer, a Shading Unitcomputing true Phong Shading, a Virtual Accumulation Frame Buffer for anti-aliasing,and a. classical Frame Buffer.
1992-01-01T00:00:00ZDepth Complexity in Object-Parallel Graphics Architectures
https://diglib.eg.org:443/handle/10.2312/EGGH.EGGH92.204-222
Depth Complexity in Object-Parallel Graphics Architectures
Cox, Michael; Hanrahan, Pat
P F Lister
We consider a multiprocessor graphics architecture object-parallel if graphics primitivesare assigned to processors without regard to screen location, and if each processorcompletely renders the primitives it is assigned. Such an approach leads tothe following problem: the images rendered by all processors must be merged, orcomposited, before they can be displayed. At worst, the number of pixels that mustbe merged is a frame per processor. Perhaps there is a more parsimonious approachto pixel merging in object-parallel architectures than merging a full frame from eachprocessor.In this paper we analyze the number of pixels that must be merged in object-parallelarchitectures. Our analysis is from the perspective that the number of pixels to bemerged is a function of the depth complexity of the graphics scene to be rendered,and a function of the depth complexity of each processor's subset of the scene tobe rendered. We derive a model of depth complexity of graphics scenes rendered onobject-parallel architectures. The model is based strictly on the graphics primitivesize distribution, and on number of processors. \Ve validate the model with tracedata from a number of graphics applications, and with trace-driven simulations ofrendering on object-parallel architectures.The results of our analysis suggest some directions in design of object-parallel architectures,and suggest that our model can be used in future analysis of designtrade-offs in these architectures."
1992-01-01T00:00:00ZAnti-Aliased Line Drawing on a Distributed Cell Store System
https://diglib.eg.org:443/handle/10.2312/EGGH.EGGH92.170-187
Anti-Aliased Line Drawing on a Distributed Cell Store System
Moore, A. A.; Ng, C. M.; Bustard, D. W.
Lister, P. F.
One of the principle drawbacks with traditional parallel image composition architectures is the lack of support for transparent images. This paper introduces the Distributed Cell Store System, an architecture based on image composition principles, but which provides explicit support for transparency via its Serial Bus System. The transparency support is exploited ina scheme for the generation of smooth-edged lines,which avoids the need for any anti-aliasing calculation in software. The benefits of segmenting lines so that different segments may be rendered in parallel in different processing units are identified and quantified, and the paper concludes with a discussion on the benefits for incremental image specification systems which could be gained from implementation on such a hardware platform."
1992-01-01T00:00:00Z