EGGH86: Eurographics Workshop on Graphics Hardware 1986ISBN 3-540-18222-5https://diglib.eg.org:443/handle/10.2312/3492019-06-16T02:29:14Z2019-06-16T02:29:14ZAVLSI Chip for Ray Tracing Bicubic PatchesPulleyblank, R W.Kapenga, J.https://diglib.eg.org:443/handle/10.2312/EGGH.EGGH86.125-1402017-03-16T11:29:21Z1986-01-01T00:00:00ZAVLSI Chip for Ray Tracing Bicubic Patches
Pulleyblank, R W.; Kapenga, J.
W. Strasser
A VLSI chip for ray tracing bicubic patches in Bezier form is explored. The purpose of the chip is to calculate the intersection point of a ray with the bicubic patch to a specified level of accuracy, returning the location of the intersection on the patch and on the ray. This is done by computing the intersection of the ray with a bounding volume of the patch and repeatedly subdividing the patch until the bounding volume of subpatches hit by the ray is smaller than the accuracy requirement. There are two operating modes, one in which only the nearest intersection is found and another in which all intersections are found. This algorithm correctly handles rays tangentially intersecting a planar patch and ray intersections at a silhouette edge of the patch. Estimates indicate that such a chip could be implemented in 2 micron NMOS and could compute patch/ray intersections at the rate of one every 15 microseconds for patches that are prescaled and specified to 12 bits fixed point for each of the x, y and z components. A version capable of handling 24 bit patches could compute patch/ray intersections at the rate of one every 140 microseconds. Images drawn using a software version of the algorithm are presented and discussed.
1986-01-01T00:00:00ZTowards a Z-Buffer and Ray-Tracing Multimode System based on Parallel Architecture and VLSI chipsP.Lemy,https://diglib.eg.org:443/handle/10.2312/EGGH.EGGH86.141-1452017-03-16T11:29:21Z1986-01-01T00:00:00ZTowards a Z-Buffer and Ray-Tracing Multimode System based on Parallel Architecture and VLSI chips
P.Lemy,
W. Strasser
After the hidden surfaces algorithms for 3D rastergraphics, hardware design isthe main problem, for many applicat ions, such as : Audiovisual animat ions. CADCAM,and simulation.After a short description of our CUBI 7 system (a 3D real-time Z-buffer system),and its CRISTAL module which increases RAY-TRACING computations, we present ourhardware project based on :-Parallel architecture for RAY-TRACING, special effects ; This module is alsouseful for pre-processing the image : (rotations, clipping, perspective transform... ).-A or Z-BUFFER which will be designed on VLSI chips polygon filling will be alsodesigned with pipe-lined chips."
1986-01-01T00:00:00ZUtilization of VLSI for Creating an Active Data Base of 3-D Geometric ModelsSkyttä, J.Takala, T.https://diglib.eg.org:443/handle/10.2312/EGGH.EGGH86.083-0932017-03-16T11:29:21Z1986-01-01T00:00:00ZUtilization of VLSI for Creating an Active Data Base of 3-D Geometric Models
Skyttä, J.; Takala, T.
W. Strasser
Parallelism of geometric computation can be achieved by distributing the computation efforts according to essentially three different strategies, based on functional, spatial and structural division, respectively (Mantyla 1983). The conventional and already commercialized way to introduce parallel computation for viewing 3-D geometric models is employing functional parallelism as a pipeline for performing different sequential transformation phases of the 3-D viewing operation (Clark 1981). This approach limits the number of parallel activities to the number of separable functional computational modules. A second approach for parallelism is the division of the modeling space into separable volume elements, which can be processed independently using a suitable data structure like an octree(Kronlof 1985). The logical component structure of a model gives a third distribution strategy. Then each processor answers only to the computational needs of its assigned objects.
1986-01-01T00:00:00Z"Position Paper:Display Hardware for Boolean Expression Models"Thomas, A. L.https://diglib.eg.org:443/handle/10.2312/EGGH.EGGH86.094-1212017-03-16T11:29:21Z1986-01-01T00:00:00Z"Position Paper:Display Hardware for Boolean Expression Models"
Thomas, A. L.
W. Strasser
In any discussion of graphics hardware there appear to be two basic positions which can be adopted. The first is that of the technologist, who is primarily concerned with what it is possible to make and how to make it. The second is that of the system designer who is more interested in what it would be desirable to make. To be a designer it is necessary to have a view of the future ... or at least a view of a plausible future! This is only possible with a reasonably sound idea of what the technologists might be persuaded to provide. I suspect that most of the "images of the future" which have guided or moulded current proposals have been around for some time. In spite of this it is a good preliminary exercise to set out a brief statement of the main ideas Which lie behind current developments, before homing in on specific hardware proposals.
1986-01-01T00:00:00Z